LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits
July 2000
LF198/LF298/LF398, LF198A/LF398A
Monolithic Sample-and-Hold Circuits
General Description
The LF198/LF298/LF398 are monolithic sample-and-hold
circuits which utilize BI-FET technology to obtain ultra-high
dc accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, dc gain accuracy is
0.002% typical and acquisition time is as low as 6 µs to
0.01%. A bipolar input stage is used to achieve low offset
voltage and wide bandwidth. Input offset adjust is accom-
plished with a single pin, and does not degrade input offset
drift. The wide bandwidth allows the LF198 to be included in-
side the feedback loop of 1 MHz op amps without having sta-
bility problems. Input impedance of 10
10
Ω
allows high
source impedances to be used without degrading accuracy.
P-channel junction FET’s are combined with bipolar devices
in the output amplifier to give droop rates as low as 5 mV/min
with a 1 µF hold capacitor. The JFET’s have much lower
noise than MOS devices used in previous designs and do
not exhibit high temperature instabilities. The overall design
guarantees no feed-through from input to output in the hold
mode, even for input signals equal to the supply voltages.
Features
n
Operates from
±
5V to
±
18V supplies
n
Less than 10 µs acquisition time
n
TTL, PMOS, CMOS compatible logic input
n
0.5 mV typical hold step at C
h
= 0.01 µF
n
Low input offset
n
0.002% gain accuracy
n
Low output noise in hold mode
n
Input characteristics do not change during hold mode
n
High supply rejection ratio in sample or hold
n
Wide bandwidth
n
Space qualified, JM38510
Logic inputs on the LF198 are fully differential with low input
current, allowing direct connection to TTL, PMOS, and
CMOS. Differential threshold is 1.4V. The LF198 will operate
from
±
5V to
±
18V supplies.
An “A” version is available with tightened electrical
specifications.
Typical Connection and Performance Curve
Acquisition Time
DS005692-32
DS005692-16
Functional Diagram
DS005692-1
© 2000 National Semiconductor Corporation
DS005692
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LF198/LF298/LF398, LF198A/LF398A
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
±
18V
Supply Voltage
Power Dissipation (Package
Limitation) (Note 2)
500 mW
Operating Ambient Temperature Range
LF198/LF198A
−55˚C to +125˚C
LF298
−25˚C to +85˚C
LF398/LF398A
0˚C to +70˚C
Storage Temperature Range
−65˚C to +150˚C
Input Voltage
Equal to Supply Voltage
Logic To Logic Reference
Differential Voltage (Note 3)
+7V, −30V
Output Short Circuit Duration
Indefinite
Hold Capacitor Short
Circuit Duration
Lead Temperature (Note 4)
H package (Soldering, 10 sec.)
N package (Soldering, 10 sec.)
M package:
Vapor Phase (60 sec.)
Infrared (15 sec.)
Thermal Resistance (θ
JA
) (typicals)
H package 215˚C/W (Board mount in still air)
85˚C/W (Board mount in
400LF/min air flow)
N package
115˚C/W
M package
106˚C/W
θ
JC
(H package, typical) 20˚C/W
10 sec
260˚C
260˚C
215˚C
220˚C
Electrical Characteristics
The following specifcations apply for −V
S
+ 3.5V
≤
V
IN
≤
+V
S
− 3.5V, +V
S
= +15V, −V
S
= −15V, T
A
= T
j
= 25˚C, C
h
= 0.01 µF,
R
L
= 10 kΩ, LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified.
Parameter
Input Offset Voltage, (Note 5)
Input Bias Current, (Note 5)
Input Impedance
Gain Error
Feedthrough Attenuation Ratio
at 1 kHz
Output Impedance
“HOLD” Step, (Note 6)
Supply Current, (Note 5)
Logic and Logic Reference Input
Current
Leakage Current into Hold
Capacitor (Note 5)
Acquisition Time to 0.1%
Hold Capacitor Charging Current
Supply Voltage Rejection Ratio
Differential Logic Threshold
Input Offset Voltage, (Note 5)
Input Bias Current, (Note 5)
T
j
= 25˚C, (Note 7)
Hold Mode
∆V
OUT
= 10V, C
h
= 1000 pF
C
h
= 0.01 µF
V
IN
−V
OUT
= 2V
V
OUT
= 0
T
j
= 25˚C
T
j
= 25˚C
Full Temperature Range
T
j
= 25˚C
Full Temperature Range
5
80
0.8
4
20
5
110
1.4
1
2.4
1
2
25
75
10
80
0.8
4
20
5
110
1.4
2
2.4
2
3
25
50
µs
µs
mA
dB
V
mV
mV
nA
nA
30
100
30
200
pA
T
j
= 25˚C, “HOLD” mode
Full Temperature Range
T
j
= 25˚C, C
h
= 0.01 µF, V
OUT
= 0
T
j
≥25˚C
T
j
= 25˚C
0.5
4.5
2
0.5
2
4
2.0
5.5
10
1.0
4.5
2
0.5
4
6
2.5
6.5
10
Ω
Ω
mV
mA
µA
T
j
= 25˚C
Full Temperature Range
T
j
= 25˚C
Full Temperature Range
T
j
= 25˚C
T
j
= 25˚C, R
L
= 10k
Full Temperature Range
T
j
= 25˚C, C
h
= 0.01 µF
86
96
10
10
Conditions
Min
LF198/LF298
Typ
1
5
Max
3
5
25
75
Min
LF398
Typ
2
10
10
10
Units
Max
7
10
50
100
mV
mV
nA
nA
Ω
0.01
0.02
%
%
dB
0.002
0.005
0.02
80
0.004
90
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2
LF198/LF298/LF398, LF198A/LF398A
Electrical Characteristics
The following specifcations apply for −V
S
+ 3.5V
≤
V
IN
≤
+V
S
− 3.5V, +V
S
= +15V, −V
S
= −15V, T
A
= T
j
= 25˚C, C
h
= 0.01 µF,
R
L
= 10 kΩ, LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified.
Parameter
Input Impedance
Gain Error
Feedthrough Attenuation Ratio
at 1 kHz
Output Impedance
“HOLD” Step, (Note 6)
Supply Current, (Note 5)
Logic and Logic Reference Input
Current
Leakage Current into Hold
Capacitor (Note 5)
Acquisition Time to 0.1%
Hold Capacitor Charging Current
Supply Voltage Rejection Ratio
Differential Logic Threshold
T
j
= 25˚C, (Note 7)
Hold Mode
∆V
OUT
= 10V, C
h
= 1000 pF
C
h
= 0.01 µF
V
IN
−V
OUT
= 2V
V
OUT
= 0
T
j
= 25˚C
90
0.8
4
20
5
110
1.4
2.4
90
0.8
6
25
4
20
5
110
1.4
2.4
6
25
µs
µs
mA
dB
V
30
100
30
100
pA
T
j
= 25˚C, “HOLD” mode
Full Temperature Range
T
j
= 25˚C, C
h
= 0.01µF, V
OUT
= 0
T
j
≥25˚C
T
j
= 25˚C
0.5
4.5
2
0.5
1
4
1
5.5
10
1.0
4.5
2
0.5
1
6
1
6.5
10
Ω
Ω
mV
mA
µA
T
j
= 25˚C
T
j
= 25˚C, R
L
= 10k
Full Temperature Range
T
j
= 25˚C, C
h
= 0.01 µF
86
96
Conditions
Min
LF198A
Typ
10
10
LF398A
Max
0.005
0.01
86
90
Min
Typ
10
10
Units
Max
Ω
0.005
0.01
%
%
dB
0.002
0.004
Note 1:
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
,
θ
JA
, and the ambient temperature, T
A
. The maximum
allowable power dissipation at any temperature is P
D
= (T
JMAX
− T
A
)/θ
JA
, or the number given in the Absolute Maximum Ratings, whichever is lower. The maximum
junction temperature, T
JMAX
, for the LF198/LF198A is 150˚C; for the LF298, 115˚C; and for the LF398/LF398A, 100˚C.
Note 3:
Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without
causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the nega-
tive supply.
Note 4:
See AN-450 “Surface Mounting Methods and their effects on Product Reliability” for other methods of soldering surface mount devices.
Note 5:
These parameters guaranteed over a supply voltage range of
±
5 to
±
18V, and an input range of −V
S
+ 3.5V
≤
V
IN
≤
+V
S
− 3.5V.
Note 6:
Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step
with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value.
Note 7:
Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can
be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range.
Note 8:
A military RETS electrical test specification is available on request. The LF198 may also be procured to Standard Military Drawing
#5962-8760801GA
or to
MIL-STD-38510 part ID JM38510/12501SGA.
Typical Performance Characteristics
Aperture Time
(Note 9)
Dielectric Absorption
Error in Hold Capacitor
Dynamic Sampling Error
DS005692-19
DS005692-17
DS005692-18
Note 9:
See Definition of Terms
3
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LF198/LF298/LF398, LF198A/LF398A
Typical Performance Characteristics
Output Droop Rate
Hold Step
(Continued)
“Hold” Settling Time
(Note 10)
DS005692-20
DS005692-21
DS005692-22
Leakage Current into Hold
Capacitor
Phase and Gain (Input to
Output, Small Signal)
Gain Error
DS005692-23
DS005692-25
DS005692-24
Power Supply Rejection
Output Short Circuit Current
Output Noise
DS005692-26
DS005692-27
DS005692-28
Note 10:
See Definition
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4
LF198/LF298/LF398, LF198A/LF398A
Typical Performance Characteristics
Input Bias Current
(Continued)
Feedthrough Rejection Ratio
(Hold Mode)
Hold Step vs Input Voltage
DS005692-29
DS005692-30
DS005692-31
Output Transient at Start
of Sample Mode
Output Transient at Start
of Hold Mode
DS005692-12
DS005692-13
Logic Input Configurations
TTL & CMOS
3V
≤
V
LOGIC
(Hi State)
≤
7V
DS005692-33
Threshold = 1.4V
DS005692-34
Threshold = 1.4V
*
Select for 2.8V at pin 8
5
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