首页 > 器件类别 > 模拟混合信号IC > 放大器电路

LF351N

Operational Amplifiers - Op Amps Single Wideband JFET

器件类别:模拟混合信号IC    放大器电路   

厂商名称:ST(意法半导体)

厂商官网:http://www.st.com/

器件标准:

下载文档
LF351N 在线购买

供应商:

器件:LF351N

价格:-

最低购买:-

库存:点击查看

点击购买

器件参数
参数名称
属性值
Brand Name
STMicroelectronics
是否Rohs认证
符合
厂商名称
ST(意法半导体)
零件包装代码
DIP
包装说明
DIP, DIP8,.3
针数
8
Reach Compliance Code
not_compliant
ECCN代码
EAR99
Factory Lead Time
16 weeks
放大器类型
OPERATIONAL AMPLIFIER
架构
VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB)
0.02 µA
25C 时的最大偏置电流 (IIB)
0.0002 µA
标称共模抑制比
70 dB
频率补偿
YES
最大输入失调电流 (IIO)
0.004 µA
最大输入失调电压
13000 µV
JESD-30 代码
R-PDIP-T8
JESD-609代码
e3
长度
9.27 mm
低-偏置
YES
低-失调
NO
负供电电压上限
-18 V
标称负供电电压 (Vsup)
-15 V
功能数量
1
端子数量
8
最高工作温度
70 °C
最低工作温度
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP8,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
+-15 V
认证状态
Not Qualified
座面最大高度
5.33 mm
最小摆率
12 V/us
标称压摆率
16 V/us
最大压摆率
2.5 mA
供电电压上限
18 V
标称供电电压 (Vsup)
15 V
表面贴装
NO
技术
BIPOLAR
温度等级
COMMERCIAL
端子面层
Matte Tin (Sn) - annealed
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
标称均一增益带宽
4000 kHz
宽度
7.62 mm
文档预览
LF351
Wide bandwidth single JFET operational amplifiers
Features
Internally adjustable input offset voltage
Low power consumption
Wide common-mode (up to V
CC+
) and
differential voltage range
Low input bias and offset current
Output short-circuit protection
High input impedance JFET input stage
Internal frequency compensation
Latch up free operation
High slew rate 16 V/µs (typical)
D
SO-8
(Plastic micro package)
N
DIP8
(Plastic package)
Description
These circuits are high speed JFET input single
operational amplifiers incorporating well matched,
high voltage JFET and bipolar transistors in a
monolithic integrated circuit.
The devices feature high slew rates, low input
bias and offset currents, and low offset voltage
temperature coefficient.
Pin connections
(top view)
1
2
3
4
8
7
6
5
1 - Offset null 1
2 - Inverting input
3 - Non-inverting input
4 - V
CC
-
5 - Offset null 2
6 - Output
7 - V
CC
+
8 - N.C.
April 2008
Rev 2
1/14
www.st.com
14
Schematics
LF351
1
Schematics
Figure 1.
Schematic diagram
V
CC
Non-inverting input
Inverting
input
100
W
200
W
Output
100
W
30k
8.2k
1.3k
V
CC
Offset Null1
35k
1.3k
35k
100
W
Offset Null2
Figure 2.
Input offset voltage null circuit
2/14
LF351
Absolute maximum ratings and operating conditions
2
Table 1.
Symbol
V
CC
V
i
V
id
R
thja
Absolute maximum ratings and operating conditions
Absolute maximum ratings
Parameter
Supply voltage
(1)
Input voltage
(2)
Differential input voltage
(3)
Thermal resistance junction to ambient
(4)
SO-8
DIP8
Thermal resistance junction to case
(4)
SO-8
DIP8
Output short-circuit duration
(5)
T
stg
Storage temperature range
HBM: human body model
(6)
ESD
MM: machine model
(7)
CDM: charged device model
(8)
Value
±18
±15
±30
125
85
40
41
Infinite
-65 to +150
500
200
1.5
°C
V
V
kV
Unit
V
V
V
°C/W
R
thjc
°C/W
1. All voltage values, except differential voltage, are with respect to the zero reference level (ground) of the supply voltages
where the zero reference level is the midpoint between V
CC+
and V
CC-
.
2. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 volts, whichever is less.
3. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
4. Short-circuits can cause excessive heating and destructive dissipation. Values are typical.
5. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure
that the dissipation rating is not exceeded
6. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩ resistor
between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating.
7. Machine model: A 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the
device with no external series resistor (internal resistor < 5
Ω).
This is done for all couples of connected pin combinations
while the other pins are floating.
8. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly
to the ground through only one pin. This is done for all pins.
Table 2.
Symbol
V
CC
T
oper
Operating conditions
Parameter
Supply voltage
Operating free-air temperature range
-55 to +125
LF151
LF251
6 to 32
-40 to +105
0 to +70
LF351
Unit
V
°C
3/14
Electrical characteristics
LF351
3
Table 3.
Symbol
V
io
DV
io
I
io
I
ib
A
vd
SVR
I
CC
V
icm
CMR
I
OS
Electrical characteristics
Electrical characteristics at V
CC
= ±15 V, T
amb
= +25°C (unless otherwise specified)
Parameter
Input offset voltage (R
s
=
10kΩ)
T
min
T
amb
T
max
Input offset voltage drift
Input offset current
(1)
T
min
T
amb
T
max
Input bias current
(1)
T
min
T
amb
T
max
Large signal voltage gain
(R
L
= 2kΩ V
o
= ±10V)
,
T
min
T
amb
T
max
Supply voltage rejection ratio (R
S
=
10kΩ)
T
min
T
amb
T
max
Supply current, no load
T
min
T
amb
T
max
Input common mode voltage range
Common mode rejection ratio (R
S
=
10kΩ)
T
min
T
amb
T
max
Output short-circuit current
T
min
T
amb
T
max
Output voltage swing
R
L
= 2kΩ
R
L
= 10kΩ
T
min
T
amb
T
max
R
L
= 2kΩ
R
L
= 10kΩ
,
Slew rate, V
i
= 10V, R
L
= 2kΩ C
L
= 100pF, unity gain
Rise time, V
i
= 20mV, R
L
= 2kΩ C
L
= 100pF, unity gain
,
Overshoot, V
i
= 20mV, R
L
= 2kΩ C
L
= 100pF, unity gain
,
Gain bandwidth product, f = 100kHz, V
in
= 10mV, R
L
= 2kΩ C
L
= 100pF
,
Input resistance
Total harmonic distortion
f= 1kHz, A
v
= 20dB, R
L
= 2kΩ, C
L
=100pF, V
o
= 2V
pp
Equivalent input noise voltage
R
S
=
100Ω, f = 1KHz
Phase margin
2.5
50
25
80
80
Min. Typ. Max.
3
10
5
20
200
86
1.4
±11 +15
-12
70
70
10
10
10
12
10
12
12
16
0.1
10
4
10
12
0.01
15
45
V/µs
µs
%
MHz
Ω
%
nV
-----------
-
Hz
Unit
mV
µV/°C
10
13
100
4
200
20
pA
nA
pA
nA
V/mV
dB
3.4
3.4
mA
V
dB
86
40
60
60
mA
±V
opp
12
13.5
V
SR
t
r
K
ov
GBP
R
i
THD
e
n
∅m
Degrees
1. The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction
temperature.
4/14
LF351
Electrical characteristics
Figure 3.
Maximum peak-to-peak output
voltage versus frequency
Figure 4.
Maximum peak-to-peak output
voltage versus frequency
Figure 5.
Maximum peak-to-peak output
voltage versus frequency
Figure 6.
Maximum peak-to-peak output
voltage versus free air temp.
Figure 7.
Maximum peak-to-peak output
voltage versus load resistance
Figure 8.
Maximum peak-to-peak output
voltage versus supply voltage
5/14
查看更多>
热门器件
热门资源推荐
器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
需要登录后才可以下载。
登录取消