LatticeECP2/M Family Data Sheet
DS1006 Version 03.3, August 2008
LatticeECP2/M Family Data Sheet
Introduction
June 2008
Data Sheet DS1006
Features
■
High Logic Density for System Integration
• 6K to 95K LUTs
• 90 to 583 I/Os
■
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated gearing logic
• Source synchronous standards support
– SPI4.2, SFI4 (DDR Mode), XGMII
– High Speed ADC/DAC devices
• Dedicated DDR and DDR2 memory support
– DDR1: 400 (200MHz) / DDR2: 533 (266MHz)
• Dedicated DQS support
■
Embedded SERDES (LatticeECP2M Only)
• Data Rates 250 Mbps to 3.125 Gbps
• Up to 16 channels per device
PCI Express, Ethernet (1GbE, SGMII), OBSAI,
CPRI and Serial RapidIO.
■
sysDSP™ Block
• 3 to 42 blocks for high performance multiply and
accumulate
• Each block supports
– One 36x36, four 18X18 or eight 9X9 multipliers
■
Programmable sysI/O™ Buffer Supports
Wide Range Of Interfaces
•
•
•
•
•
•
•
•
•
•
•
LVTTL and LVCMOS 33/25/18/15/12
SSTL 3/2/18 I, II
HSTL15 I and HSTL18 I, II
PCI and Differential HSTL, SSTL
LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
1149.1 Boundary Scan compliant
Dedicated bank for configuration I/Os
SPI boot flash interface
Dual boot images supported
TransFR™ I/O for simple field updates
Soft Error Detect macro embedded
■
Flexible Memory Resources
• 55Kbits to 5308Kbits sysMEM™ Embedded
Block RAM (EBR)
– 18Kbit block
– Single, pseudo dual and true dual port
– Byte Enable Mode support
• 12K to 202Kbits distributed RAM
– Single port and pseudo dual port
■
Flexible Device Configuration
■
sysCLOCK Analog PLLs and DLLs
• Two GPLLs and up to six SPLLs per device
– Clock multiply, divide, phase & delay adjust
– Dynamic PLL adjustment
• Two general purpose DLLs per device
■
Optional Bitstream Encryption
(LatticeECP2/M “S” Versions Only)
■
System Level Support
• ispTRACY™ internal logic analyzer capability
• On-chip oscillator for initialization & general use
• 1.2V power supply
Table 1-1. LatticeECP2 (Including “S-Series”) Family Selection Guide
Device
LUTs (K)
Distributed RAM (Kbits)
EBR SRAM (Kbits)
EBR SRAM Blocks
sysDSP Blocks
18x18 Multipliers
GPLL + SPLL + DLL
Maximum Available I/O
Packages and I/O Combinations
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
190
90
93
131
193
297
131
193
331
402
331
450
339
500
500
583
ECP2-6
6
12
55
3
3
12
2+0+2
190
ECP2-12
12
24
221
12
6
24
2+0+2
297
ECP2-20
21
42
276
15
7
28
2+0+2
402
ECP2-35
32
64
332
18
8
32
2+0+2
450
ECP2-50
48
96
387
21
18
72
2+2+2
500
ECP2-70
68
136
1032
60
22
88
2+4+2
583
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1-1
DS1006
Introduction_01.7
Lattice Semiconductor
Introduction
LatticeECP2/M Family Data Sheet
Table 1-2. LatticeECP2M (Including “S-Series”) Family Selection Guide
Device
LUTs (K)
sysMEM Blocks (18kb)
Embedded Memory (Kbits)
Distributed Memory (Kbits)
sysDSP Blocks
18x18 Multipliers
GPLL+SPLL+DLL
Maximum Available I/O
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
1152-ball fpBGA (35 x 35 mm)
ECP2M20
19
66
1217
41
6
24
2+6+2
304
4 / 140
4 / 304
ECP2M35
34
114
2101
71
8
32
2+6+2
410
4 / 140
4 / 303
4 / 410
4 / 270
8 / 372
8 / 410
16 / 416
16 / 436
16 / 416
16 / 520
ECP2M50
48
225
4147
101
22
88
2+6+2
410
ECP2M70
67
246
4534
145
24
96
2+6+2
436
ECP2M100
95
288
5308
202
42
168
2+6+2
520
Packages and SERDES / I/O Combinations
Introduction
The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced
DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an
economical FPGA fabric. This combination was achieved through advances in device architecture and the use of
90nm technology.
The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M
devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked
Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced configu-
ration support, including encryption (“S” versions only) and dual boot capabilities.
The LatticeECP2M device family features high speed SERDES with PCS. These high jitter tolerance and low trans-
mission jitter SERDES with PCS blocks can be configured to support an array of popular data protocols including
PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization
settings make SERDES suitable for chip to chip and small form factor backplane applications.
The ispLEVER
®
design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis
tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to
place and route the design in the LatticeECP2/M device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP2/M
family. By using these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of
their design, increasing their productivity.
1-2
LatticeECP2/M Family Data Sheet
Architecture
August 2008
Data Sheet DS1006
Architecture Overview
Each LatticeECP2/M device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-
DSP™ Digital Signal Processing blocks, as shown in Figure 2-1. In addition, the LatticeECP2M family contains
SERDES Quads in one or more of the corners. Figure 2-2 shows the block diagram of ECP2M20 with one quad.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit
without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF
block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for
flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-
dimensional array. Only one type of block is used per row.
The LatticeECP2/M devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated
18K fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM.
In addition, LatticeECP2/M devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and
adder/accumulators, which are the building blocks for complex signal processing capabilities.
The LatticeECP2M devices feature up to 16 embedded 3.125Gbps SERDES (Serializer / Deserializer) channels.
Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic.
Each group of four SERDES channels along with its Physical Coding Sub-layer (PCS) block, creates a quad. The
functionality of the SERDES/PCS Quads can be controlled by memory cells set during device configuration or by
registers that are addressable during device operation. The registers in every quad can be programmed by a soft
IP interface, referred to as the SERDES Client Interface (SCI). These quads (up to four) are located at the corners
of the devices.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the
LatticeECP2/M devices are arranged in eight banks, allowing the implementation of a wide variety of I/O standards.
In addition, a separate I/O bank is provided for the programming interfaces. PIO pairs on the left and right edges of
the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support
to aid in the implementation of high speed source synchronous standards such as SPI4.2, along with memory
interfaces including DDR2.
Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP2/M architecture provides
two General PLLs (GPLL) and up to six Standard PLLs (SPLL) per device. In addition, each LatticeECP2/M family
member provides two DLLs per device. The GPLLs and DLLs blocks are located in pairs at the end of the bottom-
most EBR row; the DLL block is located towards the edge of the device. The SPLL blocks are located at the end of
the other EBR/DSP rows.
The configuration block that supports features such as configuration bit-stream decryption, transparent updates
and dual boot support is located toward the center of this EBR row. The Ball Grid Array (BGA) package devices in
the LatticeECP2/M family supports a sysCONFIG™ port located in the corner between banks four and five, which
allows for serial or parallel device configuration.
In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error
detect capability. The LatticeECP2/M devices use 1.2V as their core voltage.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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2-1
DS1006
Architecture_01.9
Lattice Semiconductor
Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level)
Programmable
Function Units
(PFUs)
Architecture
LatticeECP2/M Family Data Sheet
Flexible sysIO Buffers:
LVCMOS, HSTL, SSTL,
LVDS, and other standards
sysDSP Blocks
Multiply and
Accumulate Support
Pre-engineered source
synchronous support
• DDR1/2
• SPI4.2
• ADC/DAC devices
sysMEM Block RAM
18kbit Dual Port
Flexible routing optimized
for speed, cost and routability
sysCLOCK PLLs and DLLs
Frequency Synthesis and
Clock Alignment
Configuration logic, including
dual boot and encryption.
On-chip oscillator and
soft-error detection.
Configuration port
Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level)
SERDES
Flexible sysIO
Buffers:
LVCMOS, HSTL
SSTL, LVDS
Programmable
Function Units
(PFUs)
Pre-Engineered
Source Synchronous
Support
• DDR1/2
• SPI4.2
• ADC/DAC devices
Channel
3
Channel
2
Channel
1
Channel
0
DSP Blocks
Multiply & Accumulate
Support
sysCLOCK SPLLs
Configuration
Logic, Including
dual
boot
and encryption,
and soft-error detection
sysMEM Block
RAM 18kbit Dual Port
Flexible Routing
optimized for speed,
cost & routability
sysCLOCK GPLLs
& GDLLs
Frequency Synthesis
& Clock Alignment
Configuration Port
On-Chip
Oscillator
2-2
