suitable for driving large/medium scale dot matrix
LCD panels, and is used in personal computers/
work stations. Through the use of UST (Ultra Slim
TCP) technology, it is ideal for substantially
decreasing the size of the frame section of the LCD
module. When combined with the LH1530 common
driver, it can create a low power consuming, high-
resolution LCD.
240-output LCD Segment Driver IC
PIN CONNECTIONS
272-PIN TCP
Y
1
1
Y
2
Y
3
TOP VIEW
FEATURES
CHIP SURFACE
•
•
•
•
•
•
•
•
•
•
•
Number of LCD drive outputs : 240
Supply voltage for LCD drive : +10.0 to +42.0 V
Supply voltage for the logic system : +2.5 to +5.5 V
Shift clock frequency
– 25 MHz (Max.) : V
DD
= +5.0±0.5 V
– 15 MHz (Max.) : V
DD
= +3.0 to +4.5 V
– 12 MHz (Max.) : V
DD
= +2.5 to +3.0 V
Low power consumption
Low output impedance
Adopts a data bus system
8-bit/12-bit parallel input modes are selectable
with a mode (MD) pin.
Automatic transfer function of an enable signal
Automatic counting function which, in the chip
selection mode, causes the internal clock to be
stopped by automatically counting 240 bits of
input data
Package : 272-pin TCP (Tape Carrier Package)
272 V
0R
V
2R
V
3R
V
5R
V
SS
TEST
2
TEST
1
MD
SHL
FR
EIO
1
LP
DISPOFF
XCK
DI
11
DI
10
DI
9
DI
8
DI
7
DI
6
DI
5
DI
4
DI
3
DI
2
DI
1
DI
0
EIO
2
V
DD
V
5L
V
3L
V
2L
241 V
0L
Y
238
Y
239
Y
240
240
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
LH1548
PIN DESCRIPTION
PIN NO.
1 to 240
241, 272
242, 271
243, 270
244, 269
245
264
265
246, 262
247 to 258
259
260
261
263
266, 267
268
SYMBOL
Y
1
-Y
240
V
0L
, V
0R
V
2L
, V
2R
V
3L
, V
3R
V
5L
, V
5R
V
DD
SHL
MD
EIO
2
, EIO
1
DI
0
-DI
11
XCK
LP
FR
TEST
1
, TEST
2
V
SS
I/O
O
–
–
–
–
–
I
I
I/O
I
I
I
I
I
I
–
DESCRIPTION
LCD drive output
Power supply for LCD drive
Power supply for LCD drive
Power supply for LCD drive
Power supply for LCD drive
Power supply for logic system (+2.5 to +5.5 V)
Input for selecting the reading direction of display data
Mode selection input
Input/output for chip selection
Display data input
Clock input for taking display data
Control input for output of non-select level
Latch pulse input for display data
AC-converting signal input for LCD drive waveform
Test mode selection input
Ground (0 V)
BLOCK DIAGRAM
V
0R
260
272
V
2R
271
V
3R
270
V
5R
269
Y
1
1
Y
2
2
Y
239
239
Y
240
240
244 V
5L
FR 263
EIO
1
262
EIO
2
246
LEVEL
SHIFTER
ACTIVE
CONTROL
240-BIT 4-LEVEL DRIVER
243 V
3L
240
240-BIT LEVEL SHIFTER
240
242 V
2L
241 V
0L
240-BIT LINE LATCH
48
48
48
48
48
LP 261
XCK 259
SHL 264
MD 265
CONTROL
LOGIC
24
24 BITS x 2
DATA
LATCH
DATA LATCH CONTROL
SP CONVERSION & DATA CONTROL
(8 to 24 or 12 to 24)
TEST
CIRCUIT
247
DI
0
248
DI
1
249
DI
2
250
DI
3
251
DI
4
252
DI
5
253
DI
6
254
DI
7
255
DI
8
256
DI
9
257 258 266 267 245
DI
10
DI
11
TEST
1
TEST
2
V
DD
268
V
SS
2
LH1548
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION
Controls the selection or non-selection of the chip.
Following an LP signal input, and after the chip selection signal is input, a selection
signal is generated internally until 240 bits of data have been read in.
Once data input has been completed, a selection signal for cascade connection is
output, and the chip is non-selected.
SP Conversion &
Data Control
Data Latch Control
Data is retained until 24 bits have been completely input, after which they are put on the
internal data bus 24 bits at a time.
Selects the state of the data latch which reads in the data bus signals. The shift direction
is controlled by the control logic. For every 48 bits of data read in, the selection signal
shifts one bit based on the state of the control circuit.
Latches the data on the data bus. The latch state of each LCD drive output pin is
controlled by the control logic and the data latch control; 240 bits of data are read in 10
sets of 24 bits.
Line Latch
Level Shifter
4-Level Driver
All 240 bits which have been read into the data latch are simultaneously latched at the
falling edge of the LP signal, and are output to the level shifter block.
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to
the driver block.
Drives the LCD drive output pins from the latch data, and selects one of 4 levels (V
0
, V
2
,
V
3
or V
5
) based on the FR and
signals.
Controls the operation of each block. When an LP signal has been input, all blocks are
reset and the control logic waits for the selection signal output from the active control
block. Once the selection signal has been output, operation of the data latch and data
transmission is controlled, 240 bits of data are read in, and the chip is non-selected.
Test Circuit
The circuit for testing. During normal operation, it isn't activated.
Active Control
Data Latch
Control Logic
3
LH1548
INPUT/OUTPUT CIRCUITS
V
DD
I
To Internal Circuit
V
SS
(0 V)
¿Applicable pins¡
DI
11
-DI
0
, XCK, LP, SHL,
FR, MD,
,
TEST
1
, TEST
2
Fig. 1 Input Circuit
V
DD
To Internal Circuit
V
DD
V
SS
(0 V)
I
Output Signal
O
Control Signal
V
SS
(0 V)
¿Applicable pins¡
EIO
1
, EIO
2
Fig. 2 Input/Output Circuit
V
0
V
0
V
2
Control Signal 1
Control Signal 2
O
Control Signal 3
Control Signal 4
V
SS
(0 V)
V
3
V
SS
(0 V)
V
5
¿Applicable pins¡
Y
1
-Y
240
Fig. 3 LCD Drive Output Circuit
4
LH1548
FUNCTIONAL DESCRIPTION
Pin Functions
SYMBOL
V
DD
V
SS
V
0L
, V
0R
V
2L
, V
2R
V
3L
, V
3R
V
5L
, V
5R
FUNCTION
Logic system power supply pin, connected to +2.5 to +5.5 V.
Ground pin, connected to 0 V.
Bias power supply pins for LCD drive voltage
• Normally use the bias voltages set by a resistor divider.
• Ensure that voltages are set such that V
SS
≤ V
5
< V
3
< V
2
< V
0
.
• V
iL
and V
iR
(
i
=
0
,
2
,
3
,
5
) aren't connected with inside IC. Therefore, it is necessary that
these pins connect with an external power supply.
Input pins for display data
• In 8-bit parallel input mode, input data into the 8 pins, DI
7
-DI
0
. Connect DI
11
-DI
8
to V
SS
or V
DD
.
DI
11
-DI
0
• In 12-bit parallel input mode, input data into the 12 pins, DI
11
-DI
0
.
• Refer to
"RELATIONSHIP
BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT
PINS"
in Functional Operations.
Clock input pin for taking display data
• Data is read at the falling edge of the clock pulse.
Latch pulse input pin for display data
• Data is latched at the falling edge of the clock pulse.
Input pin for selecting the reading direction of display data
• When set to V
SS
level "L", data is read sequentially from Y
240
to Y
1
.
SHL
• When set to V
DD
level "H", data is read sequentially from Y
1
to Y
240
.
• Refer to
"RELATIONSHIP
BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT
PINS"
in Functional Operations.
Control input pin for output of non-select level
• The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
• When set to V
SS
level "L", the LCD drive output pins (Y
1
-Y
240
) are set to level V
5
.
• Table of truth values is shown in
"TRUTH
TABLE"
in Functional Operations.
AC signal input pin for LCD driving waveform
• The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
FR
controls the LCD drive circuit.
• Normally it inputs a frame inversion signal.
• The LCD drive output pins' output voltage levels can be set using the line latch output
