P
RODUCT
S
PECIFICATIONS
®
Integrated Circuits Group
LH28F160S3HT-L10A
Flash Memory
16M (2MB × 8/1MB × 16)
(Model No.: LHF16KA7)
Spec No.: EL127111A
Issue Date: August 29, 2000
SHARP
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LHF16KA7
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l
Handle this document carefully for it contains material protected by international copyright
law. Any reproduction, full or in part, of this material is prohibited without the express
written permission of the company.
l
When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein are designed and manufactured for the following
application areas. When using the products covered herein for the equipment listed
in Paragraph (2), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).
i
*Office electronics
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instrumentation and measuring equipment
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Machine tools
aAudiovisual equipment
*Home appliance
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Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.
-Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
*Mainframe computers
l
Tcaffic
control systems
aGas leak detectors and automatic cutoff devices
*Rescue and security equipment
@Othersafety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
aAerospace equipment
l
Communications equipment for trunk lines
l
Control equipment for the nuclear power industry
l
Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above
three Paragraphs to a sales representative of the company.
l
Please direct all queries regarding the products covered herein to a sales representative
of the company.
Rev.1.9
SHARP
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_-
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LHF16KA7
1
CONTENTS
PAGE
I INTRODUCTION ......................................................
1.1 Product Overview.. ..............................................
2 PRINCIPLES OF OPERATION ................................
2.1
Data Protection ...................................................
3 BUS OPERATION.. ..................................................
3.1 Read ...................................................................
3.2 O&put Disable ....................................................
3.3
3.4
3.5
3.6
3.7
Standby.. .............................................................
Deep Power-Down ..............................................
Read Identifier Codes Operation.. .......................
Query Operation ..................................................
Write.. ..................................................................
3
3
6
7
7
7
7
7
7
8
8
8
8
11
11
11
11
12
12
13
13
14
14
15
15
16
16
17
PAGE
5 DESIGN CONSIDERATIONS ................................ .3C
5.1 Three-Line Output Control ................................ .3C
5.2 STS and Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit Configuration
Polling ................................................................
5.3 Power Supply Decoupling ..................................
5.4 V,, Trace on Printed Circuit Boards.. ...............
5.5 Vcc, V,,,, RP# Transitions.. ..............................
5.6 Power-Up/Down Protection.. .............................
5.7 Power Dissipation .............................................
3c
3c
.3C
.31
.31
.31
6 ELECTRICAL SPECIFICATIONS.. ........................ .3i
6.1 Absolute Maximum Ratings .............................. .3i
6.2 Operating Conditions .........................................
32
6.2.1 Capacitance .................................................
32
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
AC Input/Output Test Conditions.. ............... .3Z
DC Characteristics ........................................
34
AC Characteristics - Read-Only Operations .3E
AC Characteristics - Write Operations.. ....... .3E
Alternative CE#-Controlled Writes.. ............. .41
Reset Operations ........................................
.4Z
Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit
Configuration
Performance.. ........................
.44
4E
46
1 COMMAND DEFINITIONS.. .....................................
4.1 Read Array Command .......................................
4.2 Read Identifier Codes Command ......................
4.3 Read Status Register Command.. .....................
4.4 Clear Status Register Command.. .....................
4.5 Query Command ...............................................
4.51 Block Status Register ..................................
4.5.2 CFI Query Identification StAng.. ...................
4.5.3 System Interface.lnformation.. .....................
4.5.4 Device Geometry Definition .........................
4.5.5 SCS OEM Specific Extended Query Table..
4.6 Block Erase Command.. ....................................
4.7 Full Chip Erase Command ................................
4.8 Word/Byte Write Command.. .............................
4.9 Multi Word/Byte Write Command ......................
4.10 Block Erase Suspend Command.. ...................
7 ADDITIONAL INFORMATION ................................
7.1 Ordering Information ..........................................
4.11 (Multi) Word/Byte Write Suspend Command ... 17
4.12 Set Block Lock-Bit Command.. ........................ 18
4.13 Clear Block Lock-Bits Command.. ................... 18
4.14 STS Configuration Command ......................... 19
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Rev. 1.9
SHAl?P
LHFlGKA7
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2
LH28F160S3HT-Ll OA
1 GM-BIT (2MBx8/1 MBxl6)
Smart 3 Flash MEMORY
n Smart 3 Technology
- 2.7V or 3.3V Vcc
- 2.7V, 3.3V or SV Vpp
I
I
Common Flash Interface (CFI)
- Universal & Upgradable Interface
Scalable Command Set (SCS)
n
Enhanced Data Protection Features
- Absolute Protection with VpP=GND
- Flexible Block Locking
- Erase/Write Lockout during Power
Transitions
n High Speed Write Performance
- 32 Bytes x 2 plane Page Buffer
- 2.7 @Byte Write Transfer Rate
n High Speed Read Performance
- 1OOns(3.3V*O.3V), 120ns(2.7\1-3.6V)
I
Operating Temperature
- -40°C to +85X
n Extended Cycling Capability
- 100,000 Block Erase Cycles
- 3.2 Million Block Erase Cycles/Chip
n Low Power Management
- Deep Power-Down Mode
- Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Write and Erase
- Command User Interface
- Status Register
n Industry-Standard Packaging
- 56-Lead TSOP
n ETOgTM* V Nonvolatile
Technology
Flash
n Enhanced Automated Suspend Options
- Write Suspend to Read
- Block Erase Suspend to Write
- Block Erase Suspend to Read
n High-Density Symmetrically-Blocked
Architecture
- Thirty-two 64K-byte Erasable Blocks
I
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SRAM-Compatible
User-Configurable
Write Interface
x8 or x16 Operation
n CMOS Process
(P-type silicon substrate)
n Not designed or rated as radiation
hardened
SHARP’s LH28F160S3HT-LlOA
Flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile,
*cad/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F160S3HT-LlOA
offers three levels of protection: absolute protection with V,, at
?ND, selective hardware block locking, or flexible software block locking. These alternatives give designers
Jltimate control of their code security needs.
The LH28F160S3HT-LlOA
is conformed to the flash Scalable Command Set (SCS) and the Common Flash
nterface (CFI) specification which enable universal and upgradable interface, enable the highest system/device
data transfer rates and minimize device and system-level implementation costs.
The LH28F160S3HT-LlOA
is manufactured on SHARP’s 0.35um ETOX TM* V process technology.
ndustry-standard package: the 56-Lead TSOP ideal for board constrained applications.
‘ETOX is a trademark of Intel Corporation.
It come in
Rev. 1.9
SHARP
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1 INTRODUCTION
This datasheet
contains
LH28F160S3HT-Ll OA
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
LHFlGKA7
3
write suspend mode enables the system to read data
or execute code from any other flash memory array
location.
1
1.l Product Overview
The LH28F160S3HT-Ll OA is a high-performance
16M-bit Smart 3 Flash memory organized as
2MBx80MBxl6.
The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
Smart 3’ technology provides a choice of V,, and
V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 2.7V
Vc, consumes approximately one-fifth the power of
5V Vc,. V,, at 2.7V, 3.3V and 5V eliminates the
need for a separate 12V converter, while V,,=5V
maximizes erase and write performance. In addition
to flexible erase and program voltages, the dedicated
V,, pin gives complete data protection when
Individual block locking uses a combination of bits
and WP#, Thirty-two block lock-bits, to lock ant
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) sei
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software
polling) and status maskins
(interrupt masking for background block erase, fol
example). Status polling using STS minimizes bott
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults tc
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase
(multi) word/byte write or block lock-bit configuration
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi:
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-dowr
mode. The other 3 alternate configurations are al
pulse mode for use as a system interrupt.
The access time is 100ns (tAVQv) over the extendec
temperature range (-40°C to +85”C) and Vc, suppI\
voltage range of 3.OV-3.6V. At lower V,, voltage, the
access time is 120ns (2.7V-3.6V).
The Automatic
Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
m‘ode, the typical I,,, current is 3 mA at 3.3V V,c.
When either CE,# or CE,#, and RP# pins are at V,,
the I,, CMOS standby mode is enabled. When the
RP# pin is at GND, deep power-down mode ic
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(tPHav) is required from RP# switching high until
outputs are valid. Likewise, the device has a wake
time (tPHEL) from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
Table 1. Vcc and Vpp Voltage Combinations
Offered by Smart 3 Technology
Vcc Voltage
Vpp Voltage
2.7V
2.7V, 3.3V, 5V
3.3v
3.3v, 5v
detection
Circuitry
Internal
and
VP,
VW
automatically configures the device for optimized
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
4 block erase operation erases one of the device’s
%lK-byte blocks typically within 0.41s (3.3V Vcc, 5V
VP,) independent of other blocks. Each block can be
independently erased 100,000 times (3.2 million
olock erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
A word/byte write is performed in byte increments
typically within 12.95ps (3.3V V,,, 5V VP,). A multi
word/byte write has high speed write performance of
2.7@byte (3.3V V,,, 5V VP,). (Multi) Word/byte
Rev. 1.9
