LH532048
FEATURES
•
131,072 words
×
16 bit organization
•
Access time: 100 ns (MAX.)
•
Static operation
•
TTL compatible I/O
•
Three-state outputs
•
Single +5 V power supply
•
Power consumption:
Operating: 412.5 mW (MAX.)
Standby: 550
µW
(MAX.)
•
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
44-pin, 650-mil QFJ (PLCC)
DESCRIPTION
The LH532048 is a 2M-bit mask-programmable ROM
organized as 131,072
×
16 bits. It is fabricated using
silicon-gate CMOS process technology.
40-PIN DIP
40-PIN SOP
CMOS 2M (128K
×
16) MROM
PIN CONNECTIONS
TOP VIEW
NC
CE
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
NC
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
GND
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
532048-1
Figure 1. Pin Connections for DIP and
SOP Packages
44-PIN PLCC
V
CC
D
13
D
14
D
15
A
16
A
15
A
14
NC
NC
NC
CE
TOP VIEW
6
D
12
D
11
D
10
D
9
D
8
GND
NC
D
7
D
6
D
5
D
4
7
8
9
10
11
12
13
14
15
16
17
5
4
3
2
1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
A
13
A
12
A
11
A
10
A
9
GND
NC
A
8
A
7
A
6
A
5
18 19 20 21 22 23 24 25 26 27 28
D
3
D
2
D
1
D
0
A
0
A
1
A
2
A
3
OE
NC
A
4
532048-2
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
LH532048
CMOS 2M MROM
A
16
38
A
15
37
A
14
36
A
13
35
A
12
34
3 D
15
MEMORY
MATRIX
(131,072 x 16)
4 D
14
5 D
13
6 D
12
7 D
11
8 D
10
OUTPUT BUFFER
A
9
A
8
A
7
A
6
31
29
28
27
ADDRESS BUFFER
A
11
33
A
10
32
ADDRESS DECODER
9 D
9
10 D
8
12 D
7
13 D
6
14 D
5
15 D
4
16 D
3
17 D
2
18 D
1
A
5
26
A
4
25
A
3
24
A
2
23
A
1
22
A
0
21
COLUMN SELECTOR
CE 2
CE
BUFFER
TIMING
GENERATOR
SENSE AMPLIFIER
19 D
0
OE 20
OE
BUFFER
40
V
CC
NOTE:
Pin numbers apply to the 40-pin DIP or SOP.
11 30
GND
532048-3
Figure 3. LH532048 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
– A
16
D
0
– D
15
CE
OE
Address input
Data output
Chip enable input
Output enable input
V
CC
GND
NC
Power supply (+5 V)
Ground
No connection
2
CMOS 2M MROM
LH532048
A
16
42
A
15
41
A
14
40
A
13
39
A
12
38
4 D
15
MEMORY
MATRIX
(131,072 x 16)
5 D
14
6 D
13
7 D
12
8 D
11
9 D
10
OUTPUT BUFFER
A
9
A
8
A
7
A
6
35
32
31
30
ADDRESS BUFFER
A
11
37
A
10
36
ADDRESS DECODER
10 D
9
11 D
8
14 D
7
15 D
6
16 D
5
17 D
4
18 D
3
19 D
2
20 D
1
A
5
29
A
4
28
A
3
27
A
2
26
A
1
25
A
0
24
COLUMN SELECTOR
CE 3
CE
BUFFER
TIMING
GENERATOR
SENSE AMPLIFIER
21 D
0
OE 22
OE
BUFFER
44
V
CC
NOTE:
Pin numbers apply to the 44-pin QFJ.
12 34
GND
532048-4
Figure 4. LH532048 Block Diagram
3
LH532048
CMOS 2M MROM
TRUTH TABLE
CE
OE
DATA OUTPUT
SUPPLY CURRENT
H
L
L
X
H
L
High-Z
High-Z
D
0
– D
15
Standby
Operating
Operating
NOTE:
X = H or L, High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
CC
V
IN
V
OUT
Topr
Tstg
– 0.3 to +7.0
– 0.3 to V
CC
+ 0.3
– 0.3 to V
CC
+ 0.3
0 to +70
–65 to +150
V
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input ‘High’ voltage
Input ‘Low’ voltage
Output ‘High’ voltage
Output ‘Low’ voltage
Input leakage current
Output leakage current
V
IH
V
IL
V
OH
V
OL
| I
Ll
|
| I
LO
|
I
CC1
I
CC2
I
CC3
I
CC4
I
OH
= – 400
µA
I
OL
= 2.0 mA
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
t
RC
= 100 ns
t
RC
= 1
µs
t
RC
= 100 ns
t
RC
= 1
µs
CE = V
IH
CE = V
CC
– 0.2 V
f = 1 MHz
T
A
= 25°C
2.2
– 0.3
2.4
V
CC
+ 0.3
0.8
V
V
V
0.4
10
10
75
65
70
60
3
100
10
10
V
µA
µA
mA
mA
mA
mA
mA
µA
pF
pF
1
2
2
3
3
Operating current
Standby current
Input capacitance
Output capacitance
I
SB1
I
SB2
C
IN
C
OUT
NOTES:
1. CE/OE = V
IH
2. V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
3. V
IN
= (V
CC
– 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
4
CMOS 2M MROM
LH532048
AC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Output enable delay time
Output hold time
CE to output in High-Z
OE to output in High-Z
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CHZ
t
OHZ
100
100
100
55
0
50
ns
ns
ns
ns
ns
ns
ns
1
NOTE:
1. This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input rise/fall time
Input/output reference level
Output load condition
0.4 V to 2.6 V
10 ns
1.5 V
1 TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the V
CC
pin and the GND pin.
t
RC
A
0
- A
16
t
AA
(NOTE)
CE
t
ACE
(NOTE)
OE
t
OE
(NOTE)
t
OHZ
t
OH
t
CHZ
D
0
- D
15
NOTE:
The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or t
OE
, have concluded.
DATA VALID
532048-5
Figure 5. Timing Diagram
5
