LH5PV8512
FEATURES
•
524,288 words
×
8 bit organization
•
CE access time (t
CEA
): 120 ns (MAX.)
•
Cycle time (t
RC
): 190 ns (MIN.)
•
Power supply:
+3.0 V
±
0.15 V (Operating)
+2.2 V to +3.15 V (Data retention)
•
Power consumption (MAX.):
126 mW (Operating)
95
µW
(Standby = CMOS input level)
221
µW
(Self-refresh = CMOS input level)
•
Available for address refresh,
auto-refresh, and self-refresh modes
•
2,048 refresh cycles/32 ms
•
Address non-multiple
•
Not designed or rated as radiation
hardened
•
Package:
32-pin, 525-mil SOP
•
Package material: Plastic
•
Substrate material: P-type silicon
•
Process: Silicon-gate CMOS
•
Operating temperature: 0 - 70°C
CMOS 4M (512K
×
8) Pseudo-Static RAM
DESCRIPTION
The LH5PV8512 is a 4M bit Pseudo-Static RAM with
a 524,288 word
×
8 bit organization. It is fabricated
using silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo-static operation which elimi-
nates external clock inputs, while having the same
pinout as industry standard SRAMs. Moreover, due to
the functional similariti es between PSRAMs and
SRAMs, existing 512K
×
8 SRAM sockets can be filled
with the LH5PV8512N with little or no changes. The
advantage is the cost saving realized with the lower
cost PSRAM.
The LH5PV8512 has the ability to fill the gap between
DRAM and SRAM by offering low cost, low power
standby and simple interface.
PIN CONNECTIONS
32-PIN SOP
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A
15
A
17
WE
A
13
A
8
A
9
A
11
OE/RFSH
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
5PV8512-1
TOP VIEW
Figure 1. Pin Connections
1
LH5PV8512
CMOS 4M (512K
×
8) Pseudo-Static RAM
16 V
SS
32 V
CC
A
0
12
A
1
11
A
2
10
A
3
9
A
4
8
A
5
7
A
6
A
7
A
8
A
9
A
10
6
5
27
26
23
ROW
ADDRESS
BUFFER
EXT/INT
ADDRESS
MUX.
V
BB
GENERATOR
COLUMN
ADDRESS
BUFFER
COLUMN
DECODER
SENSE
AMPS
I/O
SELECTOR
DATA
IN
BUFFER
13 I/O
0
14 I/O
1
15 I/O
2
17 I/O
3
18 I/O
4
19 I/O
5
20 I/O
6
21 I/O
7
A
11
25
A
12
4
A
13
28
A
14
3
A
15
31
A
16
2
A
17
30
A
18
1
CE 22
ROW
DECODER
MEMORY
ARRAY
DATA
OUT
BUFFER
REFRESH
ADDRESS
COUNTER
CLOCK
GENERATOR
OE/ 24
RFSH
REFRESH
CONTROLLER
REFRESH
TIMER
WE 29
5PV8512-2
Figure 2. LH5PV8512 Block Diagram
PIN DESCRIPTION
PIN NAME
FUNCTION
PIN NAME
FUNCTION
A
0
- A
18
WE
OE/RFSH
Address input
Write enable input
Output enable input
Refresh control input
CE
I/O
0
- I/O
7
V
CC
GND
Chip enable input
Data input/output
Power supply
Ground
2
CMOS 4M (512K
×
8) Pseudo-Static RAM
LH5PV8512
TRUTH TABLE
CE
OE/RFSH
WE
I/O
0 - 7
MODE
L
L
L
H
H
L
X
H
L
H
H
L
H
X
X
Output data
Input data
High-Z
High-Z
High-Z
Read
Write
CE only refresh
Auto-refresh
Standby
NOTES:
1. X = H or L
2. If RFSH = L, it is necessary to meet t
OEH
and t
OCD
.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Applied voltage on all pins
Operating temperature
Storage temperature
Output short circuit current
Power dissipation
V
T
T
OPR
T
STG
I
O
P
D
-0.5 to +4.6
0 to +70
-65 to +150
50
600
V
°C
°C
mA
mW
1
NOTE:
1. The maximum applicable voltage on any pin with respect to V
SS
.
RECOMMENDED DC OPERATING CONDITIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Supply voltage
Input voltage
V
CC
V
SS
V
IH
V
IL
2.85
0
2.4
-0.5
3.0
0
3.15
0
4.5
0.6
V
V
V
V
1
NOTE:
1. When the supply voltage falls down under the above recommended supply voltage by temporarily power-down, a wait time longer than
400 ms is necessary at V
CC
= 0 V before the next power-up. After the supply voltage rises and gets stable, a pause of 100
µs
with
CE = RFSH = V
IH
and 8 dummy cycles are also necessary after the rises.
PIN CAPACITANCE (T
A
= +25°C, f = 1 MHz, V
CC
= 3.0 V)
PARAMETER
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
NOTE
A
0
- A
18
Input capacitance
WE, OE/RFSH
CE
Input/output capacitance
I/O
0
- I/O
7
NOTE:
1. This parameter is sampled and not 100% tested.
C
IN1
C
IN2
C
IN3
C
OUT1
8
8
8
10
pF
pF
pF
pF
1
1
1
1
3
LH5PV8512
CMOS 4M (512K
×
8) Pseudo-Static RAM
DC ELECTRICAL CHARACTERISTICS (T
A
= 0 to +70°C, V
CC
= 3.0 V
±
0.15 V)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Average supply current in normal
operation
Average supply current in standby
mode
I
CC1
t
RC
= 190 ns
CE, OE, RFSH = V
IH
CE, OE, RFSH = V
CC
- 0.2 V
CE = V
IH
OE/RFSH = V
IL
CE = V
CC
- 0.2 V,
OE, RFSH = 0.2 V
40
0.5
30
0.5
mA
mA
mA
mA
1
I
CC2
Average supply current in self-refresh
cycle
I
CC3
70
mA
µA
µA
V
V
Input leakage current
I
LI
0 V
≤
V
IN
≤
V
CC
+ 0.3 V
0 V on all other pins
0 V
≤
V
OUT
≤
V
CC
+ 0.3 V
Input/output pins in High-Z
I
OUT
= -1 mA
I
OUT
= 2.1 mA
-5
5
I/O leakage current
Output HIGH voltage
Output LOW voltage
I
LO
V
OH
V
OL
-5
2.4
5
0.4
NOTE:
1. The input/output pins are in high impedance state. I
CC1
depends on the cycle time.
4
CMOS 4M (512K
×
8) Pseudo-Static RAM
LH5PV8512
AC ELECTRICAL CHARACTERISTICS
1, 2, 3, 4, 5
(T
A
= 0 to +70°C, V
CC
= 3.0 V
±
0.15 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTES
Random read, write cycle time
Random modify write cycle time
CE pulse width
CE precharge time
Address setup time
Address hold time
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
Write disable to output in Low-Z
Chip disable to output in High-Z
Output disable to output in High-Z
WE to output in High-Z
OE set up time from CE
OE hold time from CE
OE setup time from chip disable
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write disable
Data setup time from chip disable
Data hold time from write disable
Data hold time from chip disable
Transition time (rise and fall)
Refresh time interval (2,048 cycle)
Auto refresh cycle time
Refresh
Refresh
Refresh
Refresh
delay time from CE
pulse width (Auto refresh)
precharge time (Auto refresh)
pulse width (Self refresh)
t
RC
t
RMW
t
CE
t
P
t
AS
t
AH
t
RCS
t
RCH
t
CEA
t
OEA
t
CLZ
t
OLZ
t
WLZ
t
CHZ
t
OHZ
t
WHZ
t
OES
t
OEH
t
OCD
t
WP
t
WCS
t
WCH
t
DSW
t
DSC
t
DHW
t
DHC
t
T
t
REF
t
FC
t
RFD
t
FAP
t
FP
t
FAS
t
FRS
190
250
120
70
0
30
0
0
20
0
5
0
0
15
0
35
35
120
30
30
0
0
2
190
70
80
40
8
600
10,000
120
60
30
30
30
10,000
10,000
50
32
8,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ms
ns
6
6
7
7
8
8
8
8
8
8
9
9
9
9
10, 13, 14
11, 15
11, 12, 13, 14, 15
CE delay time from refresh precharge
(Self refresh)
DATA RETENTION CHARACTERISTICS
12, 13, 14, 15, 16, 17, 18, 19, 20
(T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTES
Data retention voltage
Data retention current
(V
CC
= 3.15 V, CE = V
CC
- 0.2 V, OE/RFSH = 0.2 V)
Refresh setup time
Recover time from data retention mode
V
R
I
CCDR
t
FS
t
FR
2.2
0
5
3.15
70
V
µA
ns
ms
5
