Surface Mount PIN Diode Limiter
LM102202-Q-x-301
Data Sheet
Features
•
•
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•
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Surface Mount Limiter in Compact Package:
•
8 mm L x 5 mm W x 2.5 mm H
Incorporates PIN Limiter Diodes, DC Blocks, Schottky Diode & DC Return
Wide Frequency Range (1 to 2 GHz)
Higher Average Power Handling than Plastic-Packaged Limiters (100 W CW )
Higher Peak Power Handling than Plastic-Packaged Limiters (1000 W CW)
Very Low Insertion Loss (0.35 dB) & Low Flat Leakage Power (17 dBm)
Ultra-Thin Au Termination Plating to Combat Embrittlement
RoHS Compliant
Receiver protection
Applications
Description
The LM102202-Q-x-301 Surface Mount Silicon PIN Diode Limiter is a surface mount, passive two-stage
power limiter which can operate over the frequency range of 1 to 2 GHz. It is manufactured using Aeroflex-
Metelics proven hybrid manufacturing process incorporating PIN Diodes and passive devices integrated
onto a ceramic substrate. This low profile, compact, (8 mm L x 5 mm W x 2.5 mm H) surface mount
component offers outstanding small and large signal performance. The package has a ultra-thin Au
termination plating to combat embrittlement. This product is designed for optimal small signal insertion loss
for very low receiver noise figure and excellent large-input-signal flat leakage power for effective receiver
protection from 1 to 2 GHz.
The very low thermal resistance (20 ºC/W, junction to bottom surface of package) of the PIN diodes in this
device and the presence of a Schottky detector bias current source enables it to reliably handle RF incident
power levels up to 50 dBm CW and RF peak incident power levels up to 60 dBm (25 µs pulse width, 5% duty
cycle) at T
CASE
= 85 ºC. The I layer thickness of the output stage and the design of the internal Schottky
detector current source combine to produce flat leakage of 17 dBm typical and spike leakage energy of 0.5
ergs, typical. No external control signals are required. This limiter module includes internal DC blocking
capacitors in the RF signal path, as well as an internal DC return path.
Environmental Capabilities
The LM102202-Q-x-301 limiter is compatible with high volume, surface mount, solder re-flow manufacturing
methods. This product is durable and capable of reliably operating in military, commercial, and industrial
environments The device is RoHS compliant and is available in tube or tape-reel. The LM102202-Q-x-301
limiter is capable of meeting the environmental requirements of MIL-STD-750 and MIL-STD-202.
ESD and Moisture Sensitivity Level Rating
As are all semiconductor devices, PIN diode limiters are susceptible to damage from ESD events. The ESD
rating for this device is Class 0 (HBM). The moisture sensitivity level rating for this device is MSL 1.
1
Document No. DS 13814 Rev.J, ECN 13784
Revision Date: 05/29/2014
PIN Diode Limiter
Limiter Schematic – LM102202-Q-A-301
Limiter Schematic – LM102202-Q-B-301
Limiter Schematic – LM102202-Q-C-301
Pinout
2
603-641-3800 • 888-641-SEMI (7364) • metelics-sales@aeroflex.com • www.aeroflex.com/metelics
Document No. DS 13814 Rev.J, ECN 13784
Revision Date: 05/29/2014
PIN Diode Limiter
Absolute Maximum Ratings
Parameter
Operating Temperature
Storage Temperature
Junction Temperature
Assembly Temperature
RF Peak Incident Power Handling
@ Z
0
= 50
Ω
, T
A
= +25ºC as measured in Aeroflex evaluation board (Unless Otherwise Defined)
Conditions
Absolute Maximum Value
-65 ºC to 150 ºC
-65 ºC to 150 ºC
175 ºC
260 ºC
60 dBm
t = 30 s
T
CASE
= 85 ºC, source and load VSWR < 1.2:1,
RF pulse width = 25 µs, duty cycle = 5%,
derate linearly to 0 W at T
CASE
= 150 ºC (note 1)
T
CASE
= 85 ºC, source and load VSWR < 1.2:1,
derate linearly to 0 W at T
CASE
= 150 ºC (note 1)
Junction to bottom surface of package
Voltage Breakdown at 10µA
RF CW Incident Power Handling
Θ
JC
Thermal Resistance
RF Input & Output DC Block
Capacitor Voltage Breakdown
Notes:
1
50 dBm
25 ºC/W
45 V DC
T
CASE
is defined as the temperature of the bottom surface of the package
LM102202-Q-x-301 Electrical Specifications
Parameter
Frequency
Insertion Loss
Insertion Loss Rate of Change
vs. Operating Temperature
Return Loss
Input 1 dB Compression Point
2
ND
Harmonic
Peak Incident Power
CW Incident Power
Flat Leakage Power
Spike Leakage Energy
Symbol
F
IL
ΔIL
RL
IP
1dB
2F
0
P
inc
(Pk)
P
inc
(CW)
FL
SL
Z
0
= 50
Ω
, T
A
= 25ºC as measured in Aeroflex evaluation board (Unless Otherwise Defined)
Test Conditions
1 GHz
≤
F
≤
2 GHz
Min.
Value
1
0.35
0.005
18
8
20
10
-50
12
-45
60
50
17
0.5
19.5
0.6
Typ.
Value
Max.
Value
2
0.5
Units
GHz
dB
dB/ºC
dB
dBm
dBc
dBm
dBm
dBm
erg
1 GHz
≤
F
≤
2 GHz, P
in
= 0 dBm
1 GHz
≤
F
≤
2 GHz, P
in
≤
-10 dBm
1 GHz
≤
F
≤
2 GHz, P
in
= 0 dBm
1 GHz
≤
F
≤
2 GHz
P
in
= 0 dBm, F
0
= 2.0 GHz
RF Pulse Width = 25 µs, duty cycle = 5%,
t
rise
≤
2 µs, t
fall
≤
2 µs
1 GHz
≤
F
≤
2 GHz
P
in
= 60 dBm peak, RF pulse width = 25 µs, duty
cycle = 5%, t
rise
≤
2 µs, t
fall
≤
1 µs
P
in
= 60 dBm peak, RF pulse width = 25 µs, duty
cycle = 5%
50% falling edge of RF pulse to 1 dB IL, P
IN
= 50
dBm peak, RF pulse width = 25 µs, duty cycle = 5%,
t
rise
≤
2 µs, t
fall
≤
1 µs
50% falling edge of RF pulse to 1 dB IL, P
IN
= 60
dBm peak, RF pulse width = 50 µs, duty cycle =10%,
t
rise
≤
2 µs, t
fall
≤
1 µs
1
3
µs
Recovery Time
T
R
1.5
4
µs
603-641-3800 • 888-641-SEMI (7364) • metelics-sales@aeroflex.com • www.aeroflex.com/metelics
Document No. DS 13814 Rev.J, ECN 13784
Revision Date: 05/29/2014
3
PIN Diode Limiter
Criteria for Proper Mounting on PCB
When a large signal is incident upon the input of the LM102202-Q-x-301, the impedance of the coarse
limiter diodes is forced to a low value by the charge which is injected into these diodes by the combination
of the current from the internal detector stage and the large RF voltage initially present across these diodes.
As the impedance of these diodes decreases, an increasingly large impedance mismatch with the
impedance of the transmission line to which the limiter is connected is created. Ultimately, the impedance
of the coarse limiter diodes is reduced to a few ohms or less. This mismatch creates a standing wave, with
a current maximum and voltage minimum located at the position of the coarse limiter diodes. While the large
majority of the input signal power is reflected back to its source due to the impedance mismatch, the
significant RF current that flows at the current maximum causes Joule heating to occur in the coarse limiter
diodes. In order to maintain the junction temperature of these diodes below their maximum rated value,
there must be a path with minimal thermal resistance from the coarse diodes to the external system heat
sink. Also, there must be a minimal electrical resistance and inductance between the underside of the
limiter module package and the system ground in order to achieve maximum RF isolation between the input
and the output of the limiter module.
For these reasons, it is imperative that there are no voids in the electrical and thermal paths directly under
the coarse limiter diodes. Care must be taken when mounting the LM102202-Q-x-301 to avoid voids in the
solder joint in the area along the lengthwise axis of the package, under and between the filled vias in the
AlN substrate of the module which are shown in the diagram (above). It is also important to ensure no solder
voids exist between the limiter module RF ports and the PCB to which the limiter module is attached.
No greater than 50% of the remaining metalized area on the bottom of the package may contain solder
voids.
4
603-641-3800 • 888-641-SEMI (7364) • metelics-sales@aeroflex.com • www.aeroflex.com/metelics
Document No. DS 13814 Rev.J, ECN 13784
Revision Date: 05/29/2014
PIN Diode Limiter
Z
0
= 50
Ω
, T
CASE
= 25ºC, P
IN
= 0 dBm as measured in the Aeroflex Metelics evaluation board
(Unless Otherwise Defined)
LM102202-Q-x-301 Typical Performance
Corrected Insertion Loss vs. Frequency
(insertion loss of evaluation board
subtracted from overal insertion loss)
Return Loss vs. Frequency
CW Output Power vs. CW Input Power
Flat Leakage Output Power vs. Input Power,
Pulse width = 10 µs, Duty Cycle = 1%, f = 2 GHz
603-641-3800 • 888-641-SEMI (7364) • metelics-sales@aeroflex.com • www.aeroflex.com/metelics
Document No. DS 13814 Rev.J, ECN 13784
Revision Date: 05/29/2014
5
FPGA/CPLD
