Power ground. PGND pins must be connected together directly at the part.
Power ground. PGND pins must be connected together directly at the part.
Power ground. PGND pins must be connected together directly at the part.
Power switch input. Switch connected between SW pins and PGND pins.
Power switch input. Switch connected between SW pins and PGND pins.
Power switch input. Switch connected between SW pins and PGND pins.
Pin not connected internally.
Analog power input.
Switching frequency select input. V
IN
= 1.25MHz. Ground = 600kHz.
Connect to ground.
Function
Compensation network connection. Connected to the output of the voltage error amplifier.
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2
LM2700
Block Diagram
20012303
Detailed Description
The LM2700 utilizes a PWM control scheme to regulate the
output voltage over all load conditions. The operation can
best be understood referring to the block diagram and
Figure
1
of the
Operation
section. At the start of each cycle, the
oscillator sets the driver logic and turns on the NMOS power
device conducting current through the inductor, cycle 1 of
Figure 1
(a). During this cycle, the voltage at the V
C
pin
controls the peak inductor current. The V
C
voltage will in-
crease with larger loads and decrease with smaller. This
voltage is compared with the summation of the SW voltage
and the ramp compensation. The ramp compensation is
used in PWM architectures to eliminate the sub-harmonic
oscillations that occur during duty cycles greater than 50%.
Once the summation of the ramp compensation and switch
voltage equals the V
C
voltage, the PWM comparator resets
the driver logic turning off the NMOS power device. The
inductor current then flows through the schottky diode to the
load and output capacitor, cycle 2 of
Figure 1
(b). The NMOS
power device is then set by the oscillator at the end of the
period and current flows through the inductor once again.
The LM2700 has dedicated protection circuitry running dur-
ing normal operation to protect the IC. The Thermal Shut-
down circuitry turns off the NMOS power device when the
die temperature reaches excessive levels. The UVP com-
parator protects the NMOS power device during supply
power startup and shutdown to prevent operation at voltages
less than the minimum input voltage. The OVP comparator is
used to prevent the output voltage from rising at no loads
allowing full PWM operation over all load conditions. The
LM2700 also features a shutdown mode decreasing the
supply current to 5µA.
3
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LM2700
Absolute Maximum Ratings
(Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
IN
SW Voltage
FB Voltage
V
C
Voltage
SHDN Voltage (Note 1)
FSLCT (Note 1)
Maximum Junction Temperature
Power Dissipation(Note 3)
Lead Temperature
Vapor Phase (60 sec.)
12V
18V
7V
0.965V
≤
V
C
≤
1.565V
7V
12V
150˚C
Internally Limited
300˚C
215˚C
Infrared (15 sec.)
ESD Susceptibility (Note 4)
Human Body Model
Machine Model
220˚C
2kV
200V
Operating Conditions
Operating Junction
Temperature Range
(Note 5)
Storage Temperature
Supply Voltage
SW Voltage
−40˚C to +125˚C
−65˚C to +150˚C
2.2V to 12V
17.5V
Electrical Characteristics
Specifications in standard type face are for T
J
= 25˚C and those with
boldface type
apply over the full
Operating Tempera-
ture Range
(T
J
= −40˚C to +125˚C) Unless otherwise specified. V
IN
=2.2V and I
L
= 0A, unless otherwise specified.
Symbol
I
Q
Parameter
Quiescent Current
Conditions
FB = 2.2V (Not Switching)
FSLCT = 0V
FB = 2.2V (Not Switching)
FSLCT = V
IN
V
SHDN
= 0V
V
FB
I
CL
(Note 7)
%V
FB
/∆V
IN
I
B
V
IN
g
m
A
V
D
MAX
D
MIN
f
S
I
SHDN
I
L
R
DSON
Th
SHDN
UVP
θ
JA
Feedback Voltage
Switch Current Limit
Feedback Voltage Line
Regulation
FB Pin Bias Current
(Note 9)
Input Voltage Range
Error Amp Transconductance
∆I
= 5µA
Error Amp Voltage Gain
Maximum Duty Cycle
Minimum Duty Cycle
Switching Frequency
Shutdown Pin Current
Switch Leakage Current
Switch R
DSON
(Note 10)
SHDN Threshold
On Threshold
Off Threshold
Thermal Resistance
(Note 11)
TSSOP, package only
LLP, package only
FSLCT = Ground
FSLCT = Ground
FSLCT = V
IN
FSLCT = Ground
FSLCT = V
IN
V
SHDN
= V
IN
V
SHDN
= 0V
V
SW
= 18V
V
IN
= 2.7V, I
SW
= 2A
Output High
Output Low
1.95
1.85
0.9
480
1
78
2.2
40
155
135
85
15
30
600
1.25
0.008
−0.5
0.02
80
0.6
0.6
2.05
1.95
150
45
0.3
2.2
2.1
720
1.5
1
−1
20
150
V
IN
= 2.7V (Note 8)
2.2V
≤
V
IN
≤
12.0V
1.2285
2.55
Min
(Note 5)
Typ
(Note 6)
1.2
1.3
5
1.26
3.6
0.02
0.5
Max
(Note 5)
2
2
20
1.2915
4.3
0.07
40
12
290
Units
mA
mA
µA
V
A
%/V
nA
V
µmho
V/V
%
%
kHz
MHz
µA
µA
mΩ
V
V
V
V
˚C/W
Note 1:
This voltage should never exceed V
IN
.
Note 2:
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to
be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
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4
LM2700
Electrical Characteristics
(Continued)
Note 3:
The maximum allowable power dissipation is a function of the maximum junction temperature, T
J
(MAX), the junction-to-ambient thermal resistance,
θ
JA
,
and the ambient temperature, T
A
. See the Electrical Characteristics table for the thermal resistance. The maximum allowable power dissipation at any ambient
temperature is calculated using: P
D
(MAX) = (T
J(MAX)
− T
A
)/θ
JA
. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown.
Note 4:
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin.
Note 5:
All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% tested
or guaranteed through statistical analysis. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
All limits are used to calculate Average Outgoing Quality Level (AOQL).
Note 6:
Typical numbers are at 25˚C and represent the most likely norm.
Note 7:
Duty cycle affects current limit due to ramp generator.
Note 8:
Current limit at 0% duty cycle. See TYPICAL PERFORMANCE section for Switch Current Limit vs. V
IN
Note 9:
Bias current flows into FB pin.
Note 10:
Does not include the bond wires. Measured directly at the die.
Note 11:
Refer to National’s packaging website for more detailed thermal information and mounting techniques for the LLP and TSSOP packages.
