PR ELIMIN A RY
LM3S2110 Microcontroller
DATA SHE ET
DS-LM3S2110- 19 7 2
Copyright
©
2007 Luminary Micro, Inc.
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©
2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
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Preliminary
November 29, 2007
LM3S2110 Microcontroller
Table of Contents
About This Document .................................................................................................................... 18
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
18
18
18
18
20
25
26
27
27
27
28
28
30
31
31
32
34
34
34
35
35
35
35
35
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 20
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 33
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 39
Interrupts ............................................................................................................................ 41
JTAG Interface .................................................................................................................... 43
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
44
44
45
46
47
47
50
50
50
52
6
6.1
6.1.1
6.1.2
System Control ................................................................................................................... 54
Functional Description ............................................................................................................... 54
Device Identification .................................................................................................................. 54
Reset Control ............................................................................................................................ 54
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Table of Contents
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
57
57
59
59
60
61
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
Internal Memory ............................................................................................................... 110
Block Diagram ........................................................................................................................ 110
Functional Description ............................................................................................................. 110
SRAM Memory ........................................................................................................................ 110
Flash Memory ......................................................................................................................... 111
Flash Memory Initialization and Configuration ........................................................................... 112
Flash Programming ................................................................................................................. 112
Nonvolatile Register Programming ........................................................................................... 113
Register Map .......................................................................................................................... 113
Flash Register Descriptions (Flash Control Offset) ..................................................................... 114
Flash Register Descriptions (System Control Offset) .................................................................. 121
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.3
8.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 134
Functional Description ............................................................................................................. 134
Data Control ........................................................................................................................... 135
Interrupt Control ...................................................................................................................... 136
Mode Control .......................................................................................................................... 137
Commit Control ....................................................................................................................... 137
Pad Control ............................................................................................................................. 137
Identification ........................................................................................................................... 137
Initialization and Configuration ................................................................................................. 137
Register Map .......................................................................................................................... 138
Register Descriptions .............................................................................................................. 140
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers ................................................................................................. 175
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
175
176
176
177
178
182
182
183
183
184
184
185
185
186
10
10.1
10.2
10.3
Watchdog Timer ............................................................................................................... 211
Block Diagram ........................................................................................................................ 211
Functional Description ............................................................................................................. 211
Initialization and Configuration ................................................................................................. 212
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LM3S2110 Microcontroller
10.4
10.5
Register Map .......................................................................................................................... 212
Register Descriptions .............................................................................................................. 213
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.3
11.4
11.5
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 234
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Bit Rate Generation .................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Frame Formats .......................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
I
2
C Bus Functional Overview ....................................................................................................
Available Speed Modes ...........................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
Command Sequence Flow Charts ............................................................................................
Initialization and Configuration .................................................................................................
I
2
C Register Map .....................................................................................................................
Register Descriptions (I
2
C Master) ...........................................................................................
Register Descriptions (I2C Slave) .............................................................................................
Controller Area Network Overview ............................................................................................
Controller Area Network Features ............................................................................................
Controller Area Network Block Diagram ....................................................................................
Controller Area Network Functional Description .........................................................................
Initialization .............................................................................................................................
Operation ...............................................................................................................................
Transmitting Message Objects .................................................................................................
Configuring a Transmit Message Object ....................................................................................
235
235
235
236
237
237
238
238
239
239
239
240
241
275
275
276
276
276
277
284
285
286
312
312
313
315
316
316
316
323
324
325
338
347
347
348
349
349
350
350
350
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.3
12.4
12.5
Synchronous Serial Interface (SSI) ................................................................................ 275
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.3
13.4
13.5
13.6
Inter-Integrated Circuit (I
2
C) Interface ............................................................................ 312
14
14.1
14.2
14.3
14.4
14.4.1
14.4.2
14.4.3
14.4.4
Controller Area Network (CAN) Module ......................................................................... 347
November 29, 2007
Preliminary
5
ADI参考电路
