P RE L I M I NA R Y
LM3S613 Microcontroller
D A TA SH EET
DS -LM3S 613- 01
C opyr ight © 2006 Lumi nary Micro , Inc.
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2
Preliminary
October 8, 2006
LM3S613 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 18
About This Document..................................................................................................................... 19
Audience........................................................................................................................................................... 19
About This Manual............................................................................................................................................ 19
Related Documents .......................................................................................................................................... 19
Documentation Conventions............................................................................................................................. 19
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
Architectural Overview ....................................................................................................... 22
Product Features ................................................................................................................................. 22
Target Applications .............................................................................................................................. 26
High-Level Block Diagram ................................................................................................................... 27
Functional Overview ............................................................................................................................ 28
ARM Cortex™-M3 ............................................................................................................................... 28
Motor Control Peripherals .................................................................................................................... 28
Analog Peripherals .............................................................................................................................. 29
Serial Communications Peripherals..................................................................................................... 29
System Peripherals.............................................................................................................................. 30
Memory Peripherals............................................................................................................................. 31
Additional Features .............................................................................................................................. 32
Hardware Details ................................................................................................................................. 32
System Block Diagram ........................................................................................................................ 33
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 34
Block Diagram ..................................................................................................................................... 35
Functional Description ......................................................................................................................... 35
Serial Wire and JTAG Debug .............................................................................................................. 35
Embedded Trace Macrocell (ETM) ...................................................................................................... 36
Trace Port Interface Unit (TPIU) .......................................................................................................... 36
ROM Table .......................................................................................................................................... 36
Memory Protection Unit (MPU) ............................................................................................................ 36
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 36
3.
4.
5.
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ........................................................................................................................ 37
Interrupts ............................................................................................................................. 39
JTAG Interface .................................................................................................................... 42
Block Diagram ..................................................................................................................................... 43
Functional Description ......................................................................................................................... 43
JTAG Interface Pins............................................................................................................................. 44
JTAG TAP Controller ........................................................................................................................... 45
Shift Registers ..................................................................................................................................... 46
Operational Considerations ................................................................................................................. 46
Initialization and Configuration............................................................................................................. 47
Register Descriptions........................................................................................................................... 48
Instruction Register (IR) ....................................................................................................................... 48
Data Registers ..................................................................................................................................... 50
6.
6.1
6.1.1
System Control.................................................................................................................... 52
Functional Description ......................................................................................................................... 52
Device Identification............................................................................................................................. 52
October 8, 2006
Preliminary
3
Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ....................................................................................................................................... 52
Power Control ...................................................................................................................................... 55
Clock Control ....................................................................................................................................... 55
System Control .................................................................................................................................... 57
Initialization and Configuration............................................................................................................. 58
Register Map ....................................................................................................................................... 58
Register Descriptions........................................................................................................................... 59
7.
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
Internal Memory .................................................................................................................. 94
Block Diagram ..................................................................................................................................... 94
Functional Description ......................................................................................................................... 94
SRAM Memory .................................................................................................................................... 94
Flash Memory ...................................................................................................................................... 95
Initialization and Configuration............................................................................................................. 96
Changing Flash Protection Bits ........................................................................................................... 96
Flash Programming ............................................................................................................................. 97
Register Map ....................................................................................................................................... 97
Register Descriptions........................................................................................................................... 98
8.
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs) ........................................................................ 108
Block Diagram ................................................................................................................................... 109
Functional Description ....................................................................................................................... 109
Data Register Operation .................................................................................................................... 110
Data Direction .................................................................................................................................... 111
Interrupt Operation............................................................................................................................. 111
Mode Control ..................................................................................................................................... 112
Pad Configuration .............................................................................................................................. 112
Identification....................................................................................................................................... 112
Initialization and Configuration........................................................................................................... 112
Register Map ..................................................................................................................................... 114
Register Descriptions......................................................................................................................... 115
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers .................................................................................................. 146
Block Diagram ................................................................................................................................... 147
Functional Description ....................................................................................................................... 147
GPTM Reset Conditions .................................................................................................................... 147
32-Bit Timer Operating Modes........................................................................................................... 147
16-Bit Timer Operating Modes........................................................................................................... 149
Initialization and Configuration........................................................................................................... 153
32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 153
32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 154
16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 154
16-Bit Input Edge Count Mode .......................................................................................................... 154
16-Bit Input Edge Timing Mode ......................................................................................................... 155
16-Bit PWM Mode.............................................................................................................................. 155
Register Map ..................................................................................................................................... 156
Register Descriptions......................................................................................................................... 157
10.
10.1
10.2
10.3
10.4
Watchdog Timer ................................................................................................................ 178
Block Diagram ................................................................................................................................... 178
Functional Description ....................................................................................................................... 179
Initialization and Configuration........................................................................................................... 179
Register Map ..................................................................................................................................... 179
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Preliminary
October 8, 2006
LM3S613 Data Sheet
10.5
Register Descriptions......................................................................................................................... 180
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.3.1
11.3.2
11.4
11.5
Analog-to-Digital Converter (ADC) .................................................................................. 201
Block Diagram ................................................................................................................................... 202
Functional Description ....................................................................................................................... 202
Sample Sequencers .......................................................................................................................... 202
Module Control .................................................................................................................................. 203
Hardware Sample Averaging Circuit.................................................................................................. 204
Analog-to-Digital Converter ............................................................................................................... 204
Test Modes ........................................................................................................................................ 204
Internal Temperature Sensor ............................................................................................................. 204
Initialization and Configuration........................................................................................................... 204
Module Initialization ........................................................................................................................... 205
Sample Sequencer Configuration ...................................................................................................... 205
Register Map ..................................................................................................................................... 205
Register Descriptions......................................................................................................................... 206
12.
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 231
Block Diagram ................................................................................................................................... 232
Functional Description ....................................................................................................................... 232
Transmit/Receive Logic ..................................................................................................................... 232
Baud-Rate Generation ....................................................................................................................... 233
Data Transmission ............................................................................................................................. 234
FIFO Operation .................................................................................................................................. 234
Interrupts............................................................................................................................................ 234
Loopback Operation .......................................................................................................................... 235
Initialization and Configuration........................................................................................................... 235
Register Map ..................................................................................................................................... 236
Register Descriptions......................................................................................................................... 237
13.
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................. 267
Block Diagram ................................................................................................................................... 267
Functional Description ....................................................................................................................... 268
Bit Rate Generation ........................................................................................................................... 268
FIFO Operation .................................................................................................................................. 268
Interrupts............................................................................................................................................ 268
Frame Formats .................................................................................................................................. 269
Initialization and Configuration........................................................................................................... 276
Register Map ..................................................................................................................................... 277
Register Descriptions......................................................................................................................... 278
14.
14.1
14.2
14.2.1
14.2.2
14.3
14.4
14.5
14.6
Inter-Integrated Circuit (I2C) Interface ............................................................................ 302
Block Diagram ................................................................................................................................... 302
Functional Description ....................................................................................................................... 302
I
2
C Bus Functional Overview ............................................................................................................. 303
Available Speed Modes ..................................................................................................................... 310
Initialization and Configuration........................................................................................................... 311
Register Map ..................................................................................................................................... 312
Register Descriptions (I2C Master).................................................................................................... 312
Register Descriptions (I2C Slave)...................................................................................................... 326
15.
15.1
15.2
Analog Comparator........................................................................................................... 334
Block Diagram ................................................................................................................................... 334
Functional Description ....................................................................................................................... 334
October 8, 2006
Preliminary
5
RF/无线
