LM5026 Active Clamp Current Mode PWM Controller
January 15, 2009
LM5026
Active Clamp Current Mode PWM Controller
General Description
The LM5026 PWM controller contains all of the features nec-
essary to implement power converters utilizing the active
clamp / reset technique with current mode control. With the
active clamp technique, higher efficiencies and greater power
densities can be realized compared to conventional catch
winding or RDC clamp / reset techniques. Two control outputs
are provided, the main power switch control (OUT_A) and the
active clamp switch control (OUT_B). The device can be con-
figured to control either a P-Channel or N-Channel clamp
switch. The main gate driver features a compound configu-
ration, consisting of both MOS and Bipolar devices, providing
superior gate drive characteristics. The LM5026 can be con-
figured to operate with bias voltages over a wide input range
of 8V to 100V. Additional features include programmable
maximum duty cycle, line under-voltage lockout, cycle-by-cy-
cle current limit, hiccup mode fault operation with adjustable
timeout delay, PWM slope compensation, soft-start, 1MHz
capable oscillator with synchronization input / output capabil-
ity, precision reference and thermal shutdown.
Features
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Current Mode Control
Internal 100V Start-up Bias Regulator
3A Compound Main Gate Driver
High Bandwidth Opto-coupler Interface
Programmable Line Under-Voltage Lockout (UVLO) with
Adjustable Hysteresis
Versatile Dual Mode Over-Current Protection with hiccup
delay timer
Programmable Overlap or Deadtime between the Main
and Active Clamp Outputs
Programmable Maximum Duty Cycle Clamp
Programmable Soft-start
Leading Edge Blanking
Resistor Programmed 1MHz Capable Oscillator
Oscillator Sync I/O Capability
Precision 5V Reference
Packages
■
TSSOP-16
■
LLP-16 (5x5 mm) Thermally Enhanced
Typical Application Circuit
20147901
Simplified Forward Power Converter with Active Clamp Reset
© 2009 National Semiconductor Corporation
201479
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LM5026
Connection Diagrams
20147950
16-Lead LLP
20147902
16-Lead TSSOP
Ordering Information
Order Number
LM5026MT
LM5026MTX
LM5026SD
LM5026SDX
Package Type
TSSOP-16
TSSOP-16
LLP-16
LLP-16
NSC Package Drawing
MTC16
MTC16
SDA16A
SDA16A
Supplied As
92 Units per anti-static tube
2500 Units on Tape and Reel
1000 Units on Tape and Reel
4500 Units on Tape and Reel
Pin Descriptions
PIN
1
NAME
VIN
DESCRIPTION
Input Voltage Source
APPLICATION INFORMATION
Input to the Start-up Regulator. Operating input range is 13V to 100V with
transient capability to 105V. For power sources outside of this range, the
LM5026 can be biased directly at VCC by an external regulator.
An external voltage divider from the power source sets the shutdown and
standby comparator levels. When UVLO reaches the 0.4V threshold the
VCC and REF regulators are enabled. At the 1.25V threshold the SS pin is
released and the device enters the active mode.
If CS exceeds 0.5V the output pulse will be terminated, entering cycle-by-
cycle current limit. An internal switch holds CS low for 100nS after OUT_A
switches high to blank leading edge transients.
If cycle-by-cycle current limit is reached during any cycle, a 10uA current
is sourced to the RES pin capacitor. If the RES capacitor voltage reaches
2.5V, the soft-start capacitor will be fully discharged and then released with
a pull-up current of 1uA. After the first output pulse at OUT_A (when SS
=1.4V), the SS pin charging current will revert back to 50 µA.
An external resistor (RSET) sets either the overlap time or deadtime for the
active clamp output. An RSET resistor connected between TIME and
AGND produces in-phase OUT_A and OUT_B pulses with overlap. An
RSET resistor connected between TIME and REF produces out-of-phase
OUT_A and OUT_B pulses with deadtime.
Maximum output current is 10mA. Locally decouple with a 0.1µF capacitor.
2
UVLO
Line Under-Voltage Lockout
3
CS
Current Sense input for
current mode control and
current limit
Restart Timer
4
RES
5
TIME
Gate Drive Overlap or
Deadtime Control
6
7
REF
VCC
Output of 5V Reference
Output of the high voltage
If an auxiliary winding raises the voltage on this pin above the regulation
start-up regulator. The VCC setpoint, the internal start-up regulator will shutdown, thus reducing the IC
voltage is regulated to 7.6 V. power dissipation.
Main Output Driver
Output of the main switch PWM gate driver. Capable of 3A peak sink
current.
8
OUT_A
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2
LM5026
PIN
9
10
11
12
NAME
OUT_B
PGND
AGND
SS
DESCRIPTION
Active Clamp Output Driver
Power Ground
Analog Return
Soft-start
APPLICATION INFORMATION
Output of the active clamp switch gate driver. Capable of 0.5A peak source
and sink current.
Connect directly to Analog Ground
Connect directly to Power Ground.
An external capacitor and an internal 50 µA current source set the soft-start
ramp. The SS current source is reduced to 1 µA following a restart event.
The soft-stop discharge current is 50 µA.
The external opto-coupler connected to the COMP pin sources current into
an internal NPN current mirror. The PWM duty cycle is maximum with zero
input current, while 1mA reduces the duty cycle to zero. The current mirror
improves the frequency response by reducing the ac voltage across the
opto-coupler detector.
13
COMP
Input to the Pulse Width
Modulator
14
15
RT
SYNC
Oscillator Frequency Control Normally biased at 2V. The total external resistance connected between
RT and AGND sets the internal oscillator frequency.
Oscillator Synchronization
Input/Output
The internal oscillator can be synchronized to an external clock with an
external pull-down device. Multiple LM5026 devices can be synchronized
together by connection of their SYNC pins.
16
EP
DCL
Maximum Duty Cycle Control An external resistor divider connected from RT to AGND sets the maximum
output duty cycle for OUT_A.
Connect to system ground plane for reduced thermal resistance.
Exposed Pad Exposed Pad, underside of
(LLP
LLP package
Package
Only)
3
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LM5026
Block Diagram
20147912
FIGURE 1. Simplified Block Diagram
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4
LM5026
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
IN
to GND
V
CC
to GND
CS to GND
COMP Input Current
All other inputs to GND
-0.3V to 105V
-0.3V to 16V
-0.3 to 1.0V
10mA
-0.3 to 7V
ESD Rating (Note 2)
Human Body Model
Storage Temperature Range
Junction Temperature
2kV
-65°C to 150°C
150°C
(Note 1)
13 to 100V
8V to 15V
-40°C to +125°C
Operating Ratings
V
IN
Voltage
External Voltage Applied to V
CC
Operating Junction Temperature
Electrical Characteristics
Specifications with standard typeface are for T
J
= 25°C, and those with
boldface
type apply over full
Operating Junction Tem-
perature range.
V
IN
= 48V, V
CC
= 10V, RT = 30.0kΩ, R
SET
= 34.8kΩ) unless otherwise stated (Note 3)
Symbol
Startup Regulator
V
CC
Reg
I-V
IN
V
CC
Regulation
V
CC
Current Limit
Startup Regulator
Leakage (external Vcc
Supply)
No Load
(Note 4)
V
IN
= 100V
7.3
20
7.6
25
165
500
7.9
V
mA
µA
Parameter
Conditions
Min
Typ
Max
Units
Shutdown Current (Iin) UVLO = 0V
V
CC
Supply
V
CC
Under-voltage
Lockout Voltage
(positive going V
cc
)
V
CC
Under-voltage
Hysteresis
V
CC
Supply Current
(I
CC
)
Reference Supply
V
REF
Ref Voltage
Ref Current Limit
UVLO Shutdown/Standby
Undervoltage
Shutdown Threshold
Undervoltage
Shutdown Hysteresis
Undervoltage Standby
Threshold
Undervoltage Standby
Hysteresis Current
Source
Current Limit
Cycle by Cycle
Threshold Voltage
ILIM Delay to Output
CS step from 0 to 0.6V Time to
onset of OUT transition (90%)
Cgate=0
70
I
CS
= 10mA
0.45
1.21
16
0.3
I
REF
= 0 mA
4.85
10
C
gate
= 0, UVLO = 1.3V
V
CC
Reg -
220mV
1.0
350
V
CC
Reg -
120mV
1.5
450
µA
V
2.0
4.2
V
mA
5
25
20
0.4
0.1
1.25
20
5.15
50
V
mV
mA
Ref Voltage Regulation I
REF
= 0 to 10mA
0.5
V
V
1.29
24
V
µA
0.5
40
0.55
V
ns
Leading Edge Blanking
Time
CS Sink Impedance
(clocked)
100
30
130
50
ns
Ω
5
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