LM9627 Color CMOS Image Sensor VGA 30 FPS
March 2001
LM9627 Color CMOS Image Sensor VGA 30 FPS
General Description
The LM9627 is a high performance, low power, third inch VGA
CMOS Active Pixel Sensor capable of capturing color digital still
or motion images and converting them to a digital data stream.
In addition to the active pixel array, an on-chip 12 bit A/D conver-
tor, fixed pattern noise elimination circuits and a video gain
amplifier is provided. Furthermore, an integrated programmable
smart timing and control circuit allows the user maximum flexibil-
ity in adjusting integration time, active window size, gain and
frame rate. Various control, timing and power modes are also
provided.
Applications
•
•
•
•
•
•
PC Camera
Digital Still Camera
Video Conferencing
Security Cameras
Toys
Machine Vision
Key Specifications
• Array Format
• Effective Image Area
Total: 664H x 504V
Active: 648H x 488V
Total: 4.98mm x 3.78 mm
Active: 4.86 mm x 3.66 mm
1/3“
7.5µm x 7.5µm
8,10 & 12 Bit Digital
57dB
0.35%
red
green
blue
• Quantum Efficiency
• Fill Factor
• Color Mosaic
• Package
• Single Supply
• Power Consumption
• Operating Temp
14.5 kLSBs/lux.s
7.5 kLSBs/lux.s
5.1 kLSBs/lux.s
27%
47% (no micro lens)
Bayer pattern
48 LCC
3.3 V
90 mW
0 to 50
o
C
Features
•
•
•
•
•
•
•
•
•
•
Supplied with micro lenses
Video or snapshot operations
Programmable pixel clock, inter-frame and inter-line delays.
Programmable partial or full frame integration
Programmable gain adjustment
Horizontal & vertical sub-sampling (2:1 & 4:2)
Windowing
External snapshot trigger & event synchronisation signals
Auto black level compensation
Flexible digital video read-out supporting programmable:
- polarity for synchronisation and pixel clock signals
- leading edge adjustment for horizontal synchronization
2
• Optical Format
• Pixel Size
• Video Outputs
• Dynamic Range
• FPN
• Sensitivity
• Programmable via 2 wire I C compatible serial interface
• Power on reset & power down mode
System Block Diagram
Storage
lens
LM9627
12bit digital image
Digital Image
Processor
I
2
C compatible
event trigger
snapshot
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2000 National Semiconductor Corporation
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LM9627
Overall Chip Block Diagram
Bad Pixel
Detect & Correct
Horizontal Shift
Register
Column CDS
Black Level
Compensation
Digital Video
Framer
d[11:0]
pclk
hsync
vsync
Row Address
Decoder
APS Array
POR
Reset
Gen
Row Address
Gen
Vertical
Timing
AMP
12 Bit A/D
Horizontal
Timing
Gain
Control
Register Bank
I
2
C Compatible
Serial I/F
sda
sclk
sadr
Clock Gen
Controller
(sequencer)
Master Timer
Power
Control
mclk
extsync
snapshot irq
pdwn
Figure 1. Chip Block Diagram
Connection Diagram
vdd_od1
vss_od1
vdd_od3
vss_od3
extsync
vdd_pix
vsrvdd
sadr
sda
6
sclk
snapshot
resetb
pdwn
vss_dig
vdd_dig
hsync
vsync
pclk
mclk
d0
NC
7
8
9
10
11
12
13
14
15
16
17
18
5
4
3
2
1
48 47 46 45 44 43
42
41
40
39
NC
fine_i
gnd
fine_ctrl
offset
vdd_ana1
vss_ana1
vref_adc
vss_ana2
vdd_ana2
vss_od2
vdd_od2
LM9627
48 PIN LCC
31
19 20 21 22 23 24 25 26 27 28 29 30
NC
d1
d9
d2
d3
d4
d5
d6
d7
d8
d10
d11
Ordering Information
Temperature
(0°C
≤
T
A
≤ +50°C)
LM9627 CCEA
NS Package
LCC
Confidential
2
NC
38
37
36
35
34
33
32
irq
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LM9627
Typical Application Circuit
System Control
Camera Control
Serial Control Bus
16
mclk
9
resetb
10
pdwn
4
irq
8
snapshot
48
extsync
7
sclk
6
sda
5
sadr
3.3V analog
3.3V analog
37 vdd_ana1
0.1
µF
vdd_ana2 33
vss_ana2 34
3.3V digital
0.1µ
F
36 vss_ana1
3.3V digital
47 vdd_od1
0.1
µF
vdd_od2 31
vss_od2 32
0.1µF
46 vss_od1
3.3V digital
3.3Vdigital
44 vdd_od3
45 vss_od3
vdd_dig
12
0.1
µF
0.1
µF
vss_dig 11
3.3V analog
3 vdd_pix
2 vrl
LM9627
vsrvdd 1
1.0
µF
0.1
µF
3.3V analog
vdd_ana
vdd_ana
1.5kΩ
35
820Ω
0.1µF
vref_adc
fine_i 41
fine_ctrl 39
1N4148
22k
Ω
1%
2N3904
10k
Ω
1%
18
19
42
43
NC
NC
NC
NC
hsync
vsync
pclk
d10
d11
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
1.2k
Ω
1%
offset 38
4.7µF
470Ω
1%
gnd 40
13 14 15
30 29 28 27 26 25 24 23 22 21 20 17
Digital Video Bus
Figure 2. Typical Application Diagram
Scan Read Out Direction
pin 1
(0,0)
vertical scan
(0,0)
digital
out
(0,0)
horizontal scan
lens
CMOS Image Sensor
Figure 3. Scan directions and position of origin in imaging system
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LM9627
Pin Descriptions
Pin
1
2
3
4
Name
vsrvdd
vrl
vdd_pix
irq
I/O
I0
I
I
O
Typ
P
A
P
D
Description
Analog bidirectional, it should be connect to ground via a 1.0µf capacitor. This pin is the
internal charge pump voltage source.
Anti blooming pin. This pin is normally tied to ground.
3.3 volt supply for the pixel array.
Digital output, the interrupt request pin. This pin generates interrupts during snapshot
mode.
Digital input with pull down resistor. This pin is used to program different slave addresses
for the sensor in an I
2
C compatible system.
I
2
C compatible serial interface data bus. The output stage of this pin has an open drain
driver.
I
2
C compatible serial interface clock.
Digital input with pull down resistor used to activate (trigger) a snapshot sequence.
Digital input with pull up resistor. When forced to a logic 0 the sensor is reset to its default
power up state. The
resetb
signal is internally synchronized to
mclk
which must be run-
ning for a reset to occur.
Digital input with pull down resistor. When forced to a logic 1 the sensor is put into power
down mode.
0 volt power supply for the digital circuits.
3.3 volt power supply for the digital circuits.
Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con-
figured to be a master, (the default), this pin is an output and is the horizontal synchroni-
zation pulse. When the sensor’s digital video port is configured to be a slave, this pin is
an input and is the row trigger.
Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con-
figured to be a master, (the default), this pin is an output and is the vertical synchroniza-
tion pulse. When the sensor’s digital video port is configured to be a slave, this pin is an
input and is the frame trigger.
Digital output. The pixel clock.
Digital input. The sensor’s master clock input.
Digital output. Bit 0 of the digital video output bus. This output can be put into tri-state
mode.
Pin not used, do not connect.
Pin not used, do not connect.
O
D
Digital output. Bit 1 of the digital video output bus. This output can be put into tri-state
mode.
Digital output. Bit 2 of the digital video output bus. This output can be put into tri-state
mode.
Digital output. Bit 3 of the digital video output bus. This output can be put into tri-state
mode.
Digital output. Bit 4 of the digital video output bus. This output can be put into tri-state
mode.
Digital output. Bit 5 of the digital video output bus. This output can be put into tri-state
mode.
Digital output. Bit 6 of the digital video output bus. This output can be put into tri-state
mode.
5
sadr
I
D
6
7
8
sda
sclk
snapshot
IO
I
I
D
D
D
9
resetb
I
D
10
11
12
pdwn
vss_dig
vdd_dig
I
I
I
D
P
P
13
hsync
IO
D
14
vsync
IO
D
15
16
17
18
19
20
pclk
mclk
d0
NC
NC
d1
O
I
O
D
D
D
21
d2
O
D
22
d3
O
D
23
d4
O
D
24
d5
O
D
25
d6
O
D
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LM9627
Pin Descriptions
(Continued)
Pin
26
Name
d7
I/O
O
Typ
D
Description
Digital output. Bit 7 of the digital video output bus. This output can be put into tri-state
mode.
Digital output. Bit 8 of the digital video output bus. This output can be put into tri-state
mode.
Digital output. Bit 9 of the digital video output bus. This output can be put into tri-state
mode.
Digital output. Bit 10 of the digital video output bus. This output can be put into tri-state
mode.
Digital output. Bit 11 of the digital video output bus. This output can be put into tri-state
mode.
3.3 volt supply for the digital IO buffers.
0 volt supply for the digital IO buffers
3.3 volt supply for analog circuits.
0 volt supply for analog circuits.
A/D reference resistor ladder voltage. See figure 4 for equivalent circuit.
0 volt supply for analog circuits.
3.3 volt supply for analog circuits.
Analog input used to adjust the offset of the sensor. See figure 4 for equivalent circuit.
Analog output used to drive the
offset
pin.
This pin must be tied to ground.
I
A
Bias current for the fine offset adjust.
Pin not used, do not connect.
Pin not used, do not connect.
I
I
I
I
O
P
P
P
P
D
3.3 volt supply for the sensor.
0 volt supply for the sensor.
0 volt supply for the digital IO buffers
3.3 volt supply for the digital IO buffers.
Digital output. The external event synchronization signal is used to synchronize external
events in snapshot mode.
27
d8
O
D
28
d9
O
D
29
d10
O
D
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
d11
vdd_od2
vss_od2
vdd_ana2
vss_ana2
vref_adc
vss_ana1
vdd_ana1
offset
fine_ctrl
gnd
fine_i
NC
NC
vdd_od3
vss_od3
vss_od1
vdd_od1
extsync
O
I
I
I
I
I
I
I
I
O
D
P
P
P
P
A
P
P
A
A
Legend: (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog).
adc_vref
offset
800Ω
1KΩ
200Ω
Figure 4. Equivalent Circuits For
adc_ref
and
offset
pins
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