LMX5080 PLLatinum 2.7 GHz Low Power Dual Modulus Prescaler for RF Personal
Communications
PRELIMINARY
April 1999
LMX5080
PLLatinum
™
2.7 GHz Low Power Dual Modulus
Prescaler for RF Personal Communications
General Description
The LMX5080 integrated dual modulus prescaler, is de-
signed to be used in a synthesized local oscillator for
2.5 GHz wireless transceivers. It is fabricated using Nation-
al’s 0.5µ ABiCV silicon BiCMOS process. The LMX5080 con-
tains three dual modulus prescalers. Either a 128/130,
256/158 or a 512/514 prescaler can be selected for up to
2.7 Gz RF input frequencies. The prescaler inputs can be
driven either differentially, or single ended with the use of a
coupling capacitor on one of the inputs to ground. The
LMX5080 CMOS output is optimized to generate very stable,
low switching noise output signals. The LMX5080 prescaler
can be used in conjunction with a low frequency Phase Lock
Loop to form a frequency synthesizer suitable for UHF trans-
ceivers. Supply voltage can range from 2.7V to 5.5V. The
LMX5080 features low current consumption; typically 7.0 mA
at 5V V
CC
The LMX5080 is available in a 8-pin Small Outline (SOP)
surface mount plastic package.
Features
2.7V to 5.5V operation
Low current consumption: 7 mA (typ)
@
5V
−40˚C to +85˚C low noise CMOS output
Selectable dual modulus prescaler
128/130
256/258
512/514
n
8-pin small package outline (SOP)
n
n
n
n
Applications
n
2.5 GHz wireless communications systems (ISM)
n
Direct Broadcast Satellite systems (DBS)
n
Cable TV tuners (CATV)
Functional Block Diagram
DS100940-1
PLLatinum
™
is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS100940
www.national.com
Connection Diagram
Small Outline Package (SOP)
DS100940-2
NS Package Number M08A
Order Number LMX5080M, LMX5080MX
Pin Descriptions
Pin
No.
1
2
Pin
Name
IN
V
CC
I/O
I
—
Description
RF small signal prescaler input. Small signal input from the voltage controlled
oscillator
Power Supply voltage input may range from 2.7V to 5.5V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly
to the ground plane.
Divide Ratio Control. CMOS logic input. Pin functionality is described in the
Modulus Control Truth Table.
Prescaler Output. CMOS level output for connection to low frequency PLL
input.
Ground for analog and digital signals.
Modulus Control Input. High impedance CMOS logic input. Pin functionality is
described in the Modulus Control Truth Table.
Divide Ratio Control. High impedance CMOS logic input. Pin functionality is
described in the Modulus Control Truth Table.
RF small signal prescaler complementary input. In single-ended mode, a
bypass capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane. The IN and IN can be driven
differentially when the bypass capacitor is omitted.
3
4
5
6
7
8
SW1
OUT
GND
MC
SW2
IN
I
O
—
I
I
I
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Value
Parameter
Power Supply
Voltage
Voltage on any
pin with
GND = 0V
Storage
Temperature
Range
Lead Temp.
(solder 4 sec)
Symbol
V
CC
Min
−0.3
Typ
Max
6.5
Units
V
Recommended Operating
Conditions
(Note 1)
Value
Parameter
Power Supply
Voltage
Operating
Temperature
Symbol
V
CC
T
A
Min
2.7
−40
Typ
Max
5.5
+85
Units
V
˚C
V
i
−0.3
V
CC
+0.3
V
T
S
T
L
−65
+1.50
+2.60
˚C
˚C
Note 1:
“Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur. Recommended Operating Conditions indicate con-
ditions for which the device is intended to be functional, but do not guarantee
specific performance limits. Electrical Characteristics document specific mini-
mum and/or maximum performance values at specified test conditions and
are guaranteed. Typ or Typical values are for informational purposes only
which are based on design parameters or device characterization and are not
guaranteed.
Note 2:
This device is a high performance RF integrated circuit and is ESD
sensitive. Handling and assembly of this device should only be done on ESD-
free workstations.
Electrical Characteristics
(V
CC
= 5.0V, T
A
= −40˚C to +85˚C except as specified) (Note 1)
Symbol
I
CC
V
OH
V
OL
f
in
Pf
in
f
out
V
IH
V
IL
I
IH
I
IL
t
Set
IM
Input Frequency
Operational Input Signal Amplitude
Output Frequency
High-level Input Voltage (MC, SW1,
SW2)
Low-level Input Voltage (MC, SW1,
SW2)
High-level Input Current (MC, SW1,
SW2)
Low-level Input Current (MC, SW1,
SW2)
Modulus Control Set-up time. (Note 3)
Input/Output Intermodulation (Note 4)
V
IH
= 0.7 x V
CC
V
IL
= 0.3 x V
CC
SW1 = H, SW2 = H
f
in
= 2.7 GHz
−10 dBm / 50Ω AC coupled
signal delivered to input.
V
CC
= 2.7V to 5.5V.
MC = 0, MC = 1.
Fin = 2.3 GHz to 2.5 GHz.
Parameter
Power Supply Current
Output Amplitude
Z
L
= 100 kΩ//10 pF
V
CC
= 2.7V to 5.5V
AC coupled. V
CC
= 2.7V to 5.5V
V
CC
= 2.7V to 5.5V
0.9 x V
CC
0.1 x V
CC
100
−15
0.1
0.7 x V
CC
0.3 x V
CC
2700
+4
25
Condition
Value
Min
Typ
7
Max
Units
mA
V
V
MHz
dBm
MHz
V
V
uA
uA
20
−30
ns
dBc
±
1
±
1
15
−35
Note 3:
See Timing Diagram.
Note 4:
Guaranteed by design and characterization, not tested. Output frequency measured at input.
3
www.national.com
Functional Description
The basic phase-lock-loop (PLL) configuration using an ex-
ternal prescaler consists of a high-stability crystal reference
oscillator, a prescaler such as the National Semiconductor
LMX5080, a low frequency synthesizer, a voltage controlled
oscillator (VCO), and a loop filter. The frequency synthesizer
typically includes programmable reference [R] and feedback
[N] frequency dividers, a phase detector, as well as a charge
pump. The MC signal is fed back to the prescaler from either
the low frequency synthesizer, or a controller to set the pres-
caler divide ratio to N or N+2. The prescaler output fre-
quency is established by dividing the VCO signal down via
the prescaler modulus. The RF inputs to the prescalar con-
sist of the Fin and /Fin input pins which are complementary
inputs to a differential pair amplifier. This configuration can
operate to 2 GHz with an input sensitivity of −15 dBm.
Block Diagram
DS100940-3
www.national.com
4
Modulus Control Truth Table
SW1
H
H
H
L
H
L
L
L
Note:
SW1, SW2, MC: H = 0.7 x V
CC
, L = 0.3 x V
CC
.
SW2
H
H
L
H
L
H
L
L
MC
H
L
H
H
L
L
H
L
Divide Ratio
1/128
1/130
1/256
1/256
1/258
1/258
1/512
1/514
Timing Diagram
DS100940-4
5
www.national.com
