LNBH26
Dual LNBS supply and control IC with step-up and I²C interface
Features
■
■
Complete interface between LNB and I²C bus
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @
0.5 A)
Selectable output current limit by external
resistor
Compliant with main satellite receivers output
voltage specification (15 programmable levels)
Accurate built-in 22 kHz tone generator suits
widely accepted standards
22 kHz tone waveform integrity guaranteed
also at no load condition
Low drop post regulator and high efficiency
step-up PWM with integrated power N-MOS
allowing low power losses
LPM function (low power mode) to reduce
dissipation
Overload and overtemperature internal
protection with I²C diagnostic bits
LNB short-circuit dynamic protection
+/- 4 kV ESD tolerant on output power pins
QFN24 (4 x 4 mm)
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■
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Description
Intended for analog and digital dual satellite
receivers/Sat-TV, and Sat-PC cards, the LNBH26
is a monolithic voltage regulator and interface IC,
assembled in QFN24 4x4 specifically designed to
provide the 13/18 V power supply and the 22 kHz
tone signalling to the LNB down-converter in the
antenna dishes or to the multi-switch box. In this
application field, it offers a complete solution for
dual tuner satellite receivers with extremely low
component count, low power dissipation together
with simple design and I²C standard interfacing.
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Applications
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STB satellite receivers
TV satellite receivers
PC card satellite receivers
Table 1.
Device summary
Order code
LNBH26PQR
Package
QFN24 (4 x 4)
Packaging
Tape and reel
February 2012
Doc ID 022771 Rev 1
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www.st.com
38
Contents
LNBH26
Contents
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Application information (valid for each section A/B) . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
DISEQC™ data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4
Data encoding by external DiSEqC envelope control
through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LPM (low power mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DISEQC™ 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Surge protections and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FLT: Fault FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VMON: output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TMON: 22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TDET: 22 kHz tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
IMON: minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . 8
PDO: overcurrent detection on output pull-down stage . . . . . . . . . . . . . . . 8
Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 8
PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ISW: inductor switching current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
COMP: boost capacitor ESR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 9
OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
5
6
2/38
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Doc ID 022771 Rev 1
LNBH26
Contents
6.1
6.2
6.3
6.4
6.5
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1
7.2
7.3
7.4
Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 022771 Rev 1
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Block diagram
LNBH26
1
Block diagram
Figure 1.
Block diagram
DSQIN-A ADDR SCL SDA
LX-A
PWM CTRL
DSQIN-B
LX-B
I²C Digital core
Isense
PWM CTRL
PGND
VUP-A
DAC
Drop control
Tone ctrl
Diagnostics
Protections
Isense
PGND
VUP-B
Gate ctrl
VOUT-A
Linear
Regulator
Linear
Regulator
Gate ctrl
VOUT-B
DETIN-A
DSQOUT-A
Tone
detector
Current
Limit
selection
Tone
detector
DETIN-B
DSQOUT-B
BPSW-A
BPSW-B
Voltage
reference
FLT
ISEL GND
BYP VCC
AM10475v1
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Doc ID 022771 Rev 1
LNBH26
Application information (valid for each section A/B)
2
Application information (valid for each section A/B)
The LNBH26 includes two completely independent sections. Except for ISEL, V
CC
and I²C
inputs, each circuit can be separately controlled and have their independent external
components. All the specifications below must be considered equal for both sections (A/B).
This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V),
generates the voltages (V
UP
) that let the integrated LDO post-regulator (generating the 13 V
/ 18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) work with a minimum dissipated
power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at V
UP
- V
OUT
=
1 V typ.). The LDO power dissipation can be further reduced when 22 kHz tone output is
disabled by setting the LPM bit to “1” (see LPM function description). The IC is also provided
with an undervoltage lockout circuit that disables the whole circuit when the supplied V
CC
drops below a fixed threshold (4.7 V typ.). The step-up converter soft-start function reduces
the in-rush current during startup. The SS time is internally fixed at 4 ms typ. to switch from
0 to 13 V, and 6 ms typ. to switch from 0 to 18 V.
2.1
DISEQC™ data encoding (DSQIN pin)
The internal 22 kHz tone generator is factory trimmed in accordance with the DiSEqC™
standards, and can be activated in 3 different ways:
1.
2.
3.
by an external 22 kHz source DiSEqC™ data connected to the DSQIN logic pin (TTL
compatible). In this case the I²C tone control bits must be set: EXTM=TEN=1.
by an external DiSEqC™ data envelope source connected to the DSQIN logic pin. In
this case the I²C tone control bits must be set: EXTM=0 and TEN=1.
through the TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this
case the DSQIN TTL pin must be pulled HIGH and the EXTM bit set to “0”.
Each of the above solutions requires that during the 22 kHz tone activation and/or
DiSEqC™ data transmission, the LPM bit must be set to “0” [see
2.4: LPM (low power
mode)].
2.2
Data encoding by external 22 kHz tone TTL signal
In order to improve design flexibility an external tone signal can be input to the DSQIN pin by
setting the EXTM bit to “1”.
The DSQIN is a logic input pin which activates the 22 kHz tone to the V
OUT
pin, by using the
LNBH26 integrated tone generator.
The output tone waveforms are internally controlled by the LNBH26 tone generator in terms
of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is
used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz
signal is required for the proper control of the DSQIN pin function. Before sending the TTL
signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as
the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH26
activates the 22 kHz tone on the V
OUT
output with about 1 µs delay from TTL signal
activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has
expired (refer to
Figure 2).
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