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LP2998MR/NOPB

IC 1-LINE OTHER TERMINATOR, PDSO8, ROHS COMPLIANT, PLASTIC, SOP-8, Bus Terminator

器件类别:模拟混合信号IC    驱动程序和接口   

厂商名称:National Semiconductor(TI )

厂商官网:http://www.ti.com

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
National Semiconductor(TI )
包装说明
HLSOP,
Reach Compliance Code
compliant
ECCN代码
EAR99
差分输出
NO
接口集成电路类型
OTHER TERMINATOR
JESD-30 代码
R-PDSO-G8
JESD-609代码
e3
长度
4.9 mm
湿度敏感等级
3
功能数量
1
信号线数量
1
端子数量
8
最高工作温度
125 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
HLSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, HEAT SINK/SLUG, LOW PROFILE
峰值回流温度(摄氏度)
260
认证状态
Not Qualified
座面最大高度
1.68 mm
最大供电电压
5.5 V
最小供电电压
2.2 V
标称供电电压
2.5 V
表面贴装
YES
温度等级
AUTOMOTIVE
端子面层
Matte Tin (Sn)
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
3.9 mm
Base Number Matches
1
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LP2998 DDR-I and DDR-II Termination Regulator
December 15, 2009
LP2998
DDR-I and DDR-II Termination Regulator
General Description
The LP2998 linear regulator is designed to meet JEDEC
SSTL-2 and JEDEC SSTL-18 specifications for termination of
DDR1-SDRAM and DDR-II memory. The device contains a
high-speed operational amplifier to provide excellent re-
sponse to load transients. The output stage prevents shoot
through while delivering 1.5A continuous current as required
for DDR1-SDRAM termination, and 0.5A continuous current
as required for DDR-II termination. The LP2998 also incor-
porates a V
SENSE
pin to provide superior load regulation and
a V
REF
output as a reference for the chipset and DIMMs.
An additional feature found on the LP2998 is an active low
shutdown (SD) pin that provides Suspend To RAM (STR)
functionality. When SD is pulled low, the V
TT
output will tri-
state providing a high impedance output, while V
REF
remains
active. A power savings advantage can be obtained in this
mode through lower quiescent current.
Features
Source and sink current
Low output voltage offset
No external resistors required
Linear topology
Suspend to Ram (STR) functionality
Low external component count
Thermal Shutdown
Available in SO-8, PSOP-8 packages
Applications
DDR-I and DDR-II Termination Voltage
SSTL-18 Termination
SSTL-2 and SSTL-3 Termination
HSTL Termination
Typical Application Circuit
30026918
© 2009 National Semiconductor Corporation
300269
www.national.com
LP2998
Connection Diagrams
30026903
Top View
PSOP-8 Layout
30026904
Top View
SO-8 Layout
Pin Descriptions
SO-8 Pin or PSOP-8 Pin
1
2
3
4
5
6
7
8
Name
GND
SD
VSENSE
VREF
VDDQ
AVIN
PVIN
VTT
EP
Ground.
Shutdown.
Feedback pin for regulating V
TT
.
Buffered internal reference voltage of V
DDQ
/2.
Input for internal reference equal to V
DDQ
/2.
Analog input pin.
Power input pin.
Output voltage for connection to termination resistors.
Exposed pad thermal connection. Connect to soft Ground (PSOP-8 only).
Function
Ordering Information
Order Number
LP2998MA
LP2998MAX
LP2998MAE
LP2998MR
LP2998MRX
LP2998MRE
Package Type
SO-8
SO-8
SO-8
PSOP-8
PSOP-8
PSOP-8
NSC Package Drawing
M08A
M08A
M08A
MRA08A
MRA08A
MRA08A
Supplied As
95 Units per Rail
2500 Units Tape and Reel
250 Units Tape and Reel
95 Units per Rail
2500 Units Tape and Reel
250 Units Tape and Reel
www.national.com
2
LP2998
Absolute Maximum Ratings
(Note
1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PVIN, AVIN, VDDQ to GND
No pin should exceed AVIN
Storage Temp. Range
Junction Temperature
Lead Temperature (Soldering, 10 sec)
−0.3V to +6V
−65°C to +150°C
150°C
260°C
SO-8 Thermal Resistance (θ
JA
)
PSOP-8 Thermal Resistance (θ
JA
)
Minimum ESD Rating (Note
2)
151°C/W
43°C/W
1kV
Operating Range
Junction Temp. Range (Note
3)
AVIN to GND
-40°C to +125°C
2.2V to 5.5V
Electrical Characteristics
Symbol
V
REF
Voltage (DDR I)
Specifications with standard typeface are for T
J
= 25°C and limits in
boldface type
apply over the full
Operating Temperature Range
(T
J
= -40°C to +125°C) (Note
4).
Unless otherwise specified,
VIN = AVIN = PVIN = 2.5V.
Parameter
Conditions
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
PVIN = VDDQ = 1.7V
PVIN = VDDQ = 1.8V
PVIN = VDDQ = 1.9V
I
REF
= -30 to +30 µA
I
OUT
= 0A
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
I
OUT
= +/- 1.5A
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
I
OUT
= 0A, AVIN = 2.5V
PVIN = VDDQ = 1.7V
0.822
0.856
0.887
PVIN = VDDQ = 1.8V
0.874
0.908
0.939
PVIN = VDDQ = 1.9V
0.923
0.957
0.988
I
OUT
= +/- 0.5A, AVIN = 2.5V
PVIN = VDDQ = 1.7V
PVIN = VDDQ = 1.8V
PVIN = VDDQ = 1.9V
V
TT
Output Voltage Offset (V
REF
– V
TT
) for DDR I (Note
7)
I
OUT
= 0A
I
OUT
= -1.5A
I
OUT
= +1.5A
0.820
0.856
0.890
0.870
0.908
0.940
0.920
0.957
0.990
-30
-30
-30
-30
-30
-30
0
0
0
0
0
0
320
100
SD = 0V
SD = 0V
1.9
0.8
SD = 0V
V
TT
= 1.25V
1
13
3
Min
Typ
Max
Units
V
V
V
V
V
V
kΩ
V
V
V
V
V
V
V
V
V
V
V
V
mV
mV
mV
mV
mV
mV
µA
kΩ
µA
µA
V
V
µA
nA
V
REF
1.135
1.158
1.185
1.235
1.258
1.285
1.335
1.358
1.385
0.837
0.860
0.887
0.887
0.910
0.937
0.936
0.959
0.986
2.5
1.120
1.159
1.190
1.210
1.259
1.290
1.320
1.359
1.390
1.125
1.159
1.190
1.225
1.259
1.290
1.325
1.359
1.390
V
REF
Voltage (DDR II)
Z
VREF
V
REF
Output Impedance
V
TT
Output Voltage (DDR I) (Note
7)
V
TT
V
TT
Output Voltage (DDR II) (Note
7)
30
30
30
30
30
30
500
150
5
VOS
Vtt
V
TT
Output Voltage Offset (V
REF
– V
TT
) for DDR II (Note
7)
I
OUT
= 0A
I
OUT
= -0.5A
I
OUT
= +0.5A
I
Q
Z
VDDQ
I
SD
I
Q_SD
V
IH
V
IL
Iv
I
SENSE
Quiescent Current (Note
5)
VDDQ Input Impedance
Quiescent current in shutdown (Note
5)
Shutdown leakage current
Minimum Shutdown High Level
Maximum Shutdown Low Level
V
TT
leakage current in shutdown
V
SENSE
Input current
I
OUT
= 0A
115
2
10
www.national.com
LP2998
Symbol
T
SD
Parameter
Thermal Shutdown (Note
6)
Conditions
Min
Typ
165
10
Max
Units
°C
°C
T
SD_HYS
Thermal Shutdown Hysteresis
Note 1:
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions.
Note 2:
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 3:
At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at
θ
JA
= 151.2° C/W
junction to ambient with no heat sink.
Note 4:
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality
Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).
Note 5:
Quiescent current is defined as the current flow into AVIN.
Note 6:
The maximum allowable power dissipation is a function of the maximum junction temperature, T
J(MAX)
, the junction to ambient thermal resistance,
θ
JA
,
and the ambient temperature, T
A
. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal
shutdown.
Note 7:
V
TT
load regulation is tested by using a 10 ms current pulse and measuring V
TT
.
www.national.com
4
LP2998
Typical Performance Characteristics
Iq vs AV
IN
in SD
Unless otherwise specified VIN = AVIN = PVIN = 2.5V
Iq vs AV
IN
30026920
30026921
V
IH
and V
IL
V
REF
vs V
DDQ
30026922
30026924
V
TT
vs V
DDQ
I
SD
vs AV
IN
over Temperature
30026927
30026926
5
www.national.com
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