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LP3985IBPX-3.0

4.7 V FIXED POSITIVE LDO REGULATOR, 0.1 V DROPOUT, PDSO5
4.7 V 固定正电压低压差线性稳压器稳压器, 0.1 V 压差, PDSO5

器件类别:半导体    电源管理   

厂商名称:National Semiconductor(TI )

厂商官网:http://www.ti.com

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器件参数
参数名称
属性值
最小输入电压
2.5 V
最大输入电压
6 V
功能数量
1
端子数量
5
加工封装描述
SOT-23, SOP-5
each_compli
Yes
状态
Transferred
调节类型
FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
可调
FIXED
dropout_voltage1_nom
0.0600 V
最大电压差1
0.1000 V
input_voltage_absolute_max
6.5 V
jesd_30_code
R-PDSO-G5
jesd_609_code
e0
line_regulation_max
0.0071 V
moisture_sensitivity_level
1
输出数
1
erating_temperature,_tj_mi
-40 Cel
erating_temperature,_tj_max
125 Cel
最大输出电流1
0.1500 A
额定输出电压1
4.7 V
最小输出电压1
4.56 V
最大输出电压1
4.84 V
包装材料
PLASTIC/EPOXY
ckage_code
LSSOP
ckage_equivalence_code
TSOP5/6,.11,37
包装形状
RECTANGULAR
包装尺寸
SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
cking_method
TAPE AND REEL
eak_reflow_temperature__cel_
260
qualification_status
COMMERCIAL
seated_height_max
1.22 mm
sub_category
Other Regulators
表面贴装
YES
工艺
CMOS
端子涂层
TIN LEAD
端子形式
GULL WING
端子间距
0.9500 mm
端子位置
DUAL
ime_peak_reflow_temperature_max__s_
40
voltage_tolerance_max
3 %
length
2.92 mm
width
1.6 mm
文档预览
LP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator
June 2003
LP3985
Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS
Voltage Regulator
General Description
The LP3985 is designed for portable and wireless applica-
tions with demanding performance and space requirements.
The LP3985 is stable with a small 1µF
±
30% ceramic or
high-quality tantalum output capacitor. The micro SMD re-
quires the smallest possible PC board area - the total appli-
cation circuit area can be less than 2.0mm x 2.5mm, a
fraction of a 1206 case size.
The LP3985’s performance is optimized for battery powered
systems to deliver ultra low noise, extremely low dropout
voltage and low quiescent current. Regulator ground current
increases only slightly in dropout, further prolonging the
battery life.
An optional external bypass capacitor reduces the output
noise without slowing down the load transient response.
Fast start-up time is achieved by utilizing an internal
power-on circuit that actively pre-charges the bypass capaci-
tor.
Power supply rejection is better than 50 dB at low frequen-
cies and starts to roll off at 1kHz. High power supply rejection
is maintained down to low input voltage levels common to
battery operated circuits.
The device is ideal for mobile phone and similar battery
powered wireless applications. It provides up to 150 mA,
from a 2.5V to 6V input. The LP3985 consumes less than
1.5µA in disable mode and has fast turn-on time less than
200µs.
The LP3985 is available in a 5 bump small bump micro SMD,
a 5 bump large bump micro SMD, a 5 bump thin micro SMD
and a 5 pin SOT-23 package. Performance is specified for
−40˚C to +125˚C temperature range and is available in 2.5V,
2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V. 3.1V, 3.2V, 3.3V, 4.7V,
4.8V and 5.0V output voltages. For other output voltage
options between 2.5V to 5.0V or for a dual LP3985, please
contact National Semiconductor sales office.
Key Specifications
n
n
n
n
n
n
n
n
n
2.5 to 6.0V input range
150mA guaranteed output
50dB PSRR at 1kHz
@
V
IN
= V
OUT
+ 0.2V
≤1.5µA
quiescent current when shut down
Fast Turn-On time: 200 µs (typ.)
100mV maximum dropout with 150mA load
30µVrms output noise (typ) over 10Hz to 100kHz
−40 to +125˚C junction temperature range for operation
2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, 3.1V, 3.2V,
3.3V, 4.7V, 4.8V and 5.0V outputs standard
Features
n
n
n
n
n
Miniature 5-I/O micro SMD and SOT-23-5 package
Logic controlled enable
Stable with ceramic and high quality tantalum capacitors
Fast turn-on
Thermal shutdown and short-circuit current limit
Applications
n
n
n
n
CDMA cellular handsets
Wideband CDMA cellular handsets
GSM cellular handsets
Portable information appliances
Typical Application Circuit
10136402
Note: Pin Numbers in parenthesis indicate micro SMD package.
*
Optional Noise Reduction Capacitor.
© 2003 National Semiconductor Corporation
DS101364
www.national.com
LP3985
Block Diagram
10136401
Pin Description
Name
V
EN
GND
V
OUT
V
IN
BYPASS
* micro SMD
A1
B2
C1
C3
A3
SOT
3
2
5
1
4
Function
Enable Input Logic, Enable High
Common Ground
Output Voltage of the LDO
Input Voltage of the LDO
Optional Bypass Capacitor for Noise
Reduction
* The pin numbering scheme for the micro SMD package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers were
revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had VEN
as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and BYPASS as pin 5.
Connection Diagrams
SOT 23-5 Package (MF)
5 Bump micro SMD Package (BPA05, BLA05, TLA05)
10136407
Top View
See NS Package Number MF05A
10136470
Top View
See NS Package Number BPA05, BLA05, TLA05
www.national.com
2
LP3985
Ordering Information
BP refers to 0.170mm bump size, 0.900mm height for micro SMD Package
Output
Voltage (V)
2.5
2.6
2.7
2.8
2.85
2.9
3.0
3.1
3.2
3.3
4.7
5.0
Grade
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
LP3985 Supplied as 250
Units, Tape and Reel
LP3985IBP-2.5
LP3985IBP-2.6
LP3985IBP-2.7
LP3985IBP-2.8
LP3985IBP-285
LP3985IBP-2.9
LP3985IBP-3.0
LP3985IBP-3.1
LP3985IBP-3.2
LP3985IBP-3.3
LP3985IBP-4.7
LP3985IBP-5.0
LP3985 Supplied as 3000
Units, Tape and Reel
LP3985IBPX-2.5
LP3985IBPX-2.6
LP3985IBPX-2.7
LP3985IBPX-2.8
LP3985IBPX-285
LP3985IBPX-2.9
LP3985IBPX-3.0
LP3985IBPX-3.1
LP3985IBPX-3.2
LP3985IBPX-3.3
LP3985IBPX-4.7
LP3985IBPX-5.0
BL refers to 0.300mm bump size, 0.995mm height for micro SMD Package
Output
Voltage (V)
2.5
2.6
2.7
2.8
2.85
2.9
3.0
3.1
3.2
3.3
4.8
5.0
Grade
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
LP3985 Supplied as 250
Units, Tape and Reel
LP3985IBL-2.5
LP3985IBL-2.6
LP3985IBL-2.7
LP3985IBL-2.8
LP3985IBL-285
LP3985IBL-2.9
LP3985IBL-3.0
LP3985IBL-3.1
LP3985IBL-3.2
LP3985IBL-3.3
LP3985IBL-4.8
LP3985IBL-5.0
LP3985 Supplied as 3000
Units, Tape and Reel
LP3985IBLX-2.5
LP3985IBLX-2.6
LP3985IBLX-2.7
LP3985IBLX-2.8
LP3985IBLX-285
LP3985IBLX-2.9
LP3985IBLX-3.0
LP3985IBLX-3.1
LP3985IBLX-3.2
LP3985IBLX-3.3
LP3985IBLX-4.8
LP3985IBLX-5.0
TL refers to 0.300mm bump size, 0.600mm height for micro SMD Package
Output
Voltage (V)
2.5
2.6
2.7
2.8
2.85
2.9
3.0
3.1
3.2
3.3
4.8
5.0
Grade
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
LP3985 Supplied as 250
Units, Tape and Reel
LP3985ITL-2.5
LP3985ITL-2.6
LP3985ITL-2.7
LP3985ITL-2.8
LP3985ITL-285
LP3985ITL-2.9
LP3985ITL-3.0
LP3985ITL-3.1
LP3985ITL-3.2
LP3985ITL-3.3
LP3985ITL-4.8
LP3985ITL-5.0
LP3985 Supplied as 3000
Units, Tape and Reel
LP3985ITLX-2.5
LP3985ITLX-2.6
LP3985ITLX-2.7
LP3985ITLX-2.8
LP3985ITLX-285
LP3985ITLX-2.9
LP3985ITLX-3.0
LP3985ITLX-3.1
LP3985ITLX-3.2
LP3985ITLX-3.3
LP3985ITLX-4.8
LP3985ITLX-5.0
3
www.national.com
LP3985
Ordering Information
Output
Voltage (V)
2.5
2.6
2.7
2.8
2.85
2.9
3.0
3.1
3.2
3.3
4.7
5.0
Grade
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
(Continued)
For SOT Package
LP3985 Supplied as 1000
Units, Tape and Reel
LP3985IM5-2.5
LP3985IM5-2.6
LP3985IM5-2.7
LP3985IM5-2.8
LP3985IM5-285
LP3985IM5-2.9
LP3985IM5-3.0
LP3985IM5-3.1
LP3985IM5-3.2
LP3985IM5-3.3
LP3985IM5-4.7
LP3985IM5-5.0
LP3985 Supplied as 3000
Units, Tape and Reel
LP3985IM5X-2.5
LP3985IM5X-2.6
LP3985IM5X-2.7
LP3985IM5X-2.8
LP3985IM5X-285
LP3985IM5X-2.9
LP3985IM5X-3.0
LP3985IM5X-3.1
LP3985IM5X-3.2
LP3985IM5X-3.3
LP3985IM5X-4.7
LP3985IM5X-5.0
Package Marking
LCSB
LCTB
LCUB
LCJB
LCXB
LCYB
LCRB
LCZB
LDPB
LDQB
LDRB
LDSB
www.national.com
4
LP3985
Absolute Maximum Ratings
2)
(Notes 1,
Operating Ratings
(Notes 1, 2)
V
IN
V
EN
Junction Temperature
Thermal Resistance
θ
JA
(SOT23-5)
θ
JA
(micro SMD)
Maximum Power Dissipation
SOT23-5 (Note 6)
micro SMD (Note 6)
2.5 to 6V
0 to (V
IN
+0.3)
6V
−40˚C to +125˚C
220˚C/W
255˚C/W
250mW
244mW
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
IN
, V
EN
V
OUT
Junction Temperature
Storage Temperature
Lead Temp.
Pad Temp. (Note 3)
Maximum Power Dissipation
SOT23-5 (Note 4)
micro SMD (Note 4)
ESD Rating(Note 5)
Human Body Model
Machine Model
−0.3 to 6.5V
-0.3 to (V
IN
+0.3)
6.5V
150˚C
−65˚C to +150˚C
235˚C
235˚C
364mW
355mW
2kV
150V
Electrical Characteristics
Unless otherwise specified: V
IN
= V
OUT(nom)
+ 0.5V, C
IN
= 1 µF, I
OUT
= 1mA, C
OUT
= 1 µF, C
BYPASS
= 0.01µF. Typical values
and limits appearing in standard typeface are for T
J
= 25˚C. Limits appearing in
boldface type
apply over the entire junction
temperature range for operation, −40˚C to +125˚C. (Note 7) (Note 8)
Symbol
Parameter
Output Voltage
Tolerance
Line Regulation Error
∆V
OUT
Load Regulation Error
(Note 9)
Output AC Line Regulation
I
OUT
= 1mA
V
IN
= (V
OUT(nom)
+ 0.5V) to 6.0V,
For 4.7 to 5.0 options
For all other options
I
OUT
= 1 mA to 150 mA
LP3985IM5 (SOT23-5)
LP3985 (micro SMD)
V
IN
= V
OUT(nom)
+ 1V,
I
OUT
= 150 mA (Figure
1)
V
IN
= V
OUT(nom)
+ 0.2V,
f = 1 kHz,
I
OUT
= 50 mA (Figure
2)
V
IN
= V
OUT(nom)
+ 0.2V,
f = 10 kHz,
I
OUT
= 50 mA (Figure
2)
V
EN
= 1.4V, I
OUT
= 0 mA
For 4.7 to 5.0 options
For all other options
V
EN
= 1.4V, I
OUT
= 0 to 150 mA
For 4.7 to 5.0 options
For all other options
V
EN
= 0.4V
Dropout Voltage (Note 10)
I
OUT
= 1 mA
I
OUT
= 50 mA
I
OUT
= 100 mA
I
OUT
= 150 mA
I
SC
I
OUT(PK)
Short Circuit Current Limit
Peak Output Current
Output Grounded
(Steady State)
V
OUT
V
OUT(nom)
- 5%
5
Conditions
Typ
Limit
Min
−2
−3
−0.19
−0.1
Max
2
3
0.19
0.1
0.005
Units
% of
V
OUT(nom)
%/V
0.0025
0.0004
1.5
50
%/mA
0.002
mV
P-P
PSRR
Power Supply Rejection Ratio
40
dB
I
Q
Quiescent Current
100
85
155
140
0.003
0.4
20
45
60
600
550
300
165
150
µA
250
200
1.5
2
35
70
100
mA
mA
www.national.com
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