LPC1766-STK development board
Users Manual
All boards produced by Olimex are ROHS compliant
Revision Initial, October 2009
Copyright(c) 2009, OLIMEX Ltd, All rights reserved
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INTRODUCTION:
LPC1766-STK is development board with LPC1766 Cortex M3 microcon-
troller from NXP. This powerful microcontroller supports various serial interfaces
such as USB Device/Host/OTG, UART, CAN and other. On the board are avalable
audio input and output, digital accelerometer, JTAG, Ethernet, TFT LCD and mini
SD/MMC card connector. All this allows you to build a diversity of powerful appli-
cations to be used in a wide range of applications.
BOARD FEATURES:
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MCU:
LPC1766
Cortex M3, 100 Mhz, 256KB Flash, 64KB RAM, Ether-
net MAC, USB Host/ Device/OTG, x4 UARTS, CAN, SPI, SSP, I2C,
I2S, ADC, DAC, TC
LCD NOKIA 6610 128x128 x12bit color TFT with Epson LCD controller
3-axis digital accelerometer with 11 bit accuracy
temperature sensor
Ethernet 100Mbit
CAN interface and connector
USB host connector
USB device connector
USB OTG connector
two user LEDs
three user buttons
joystick
potentiometer
micro SD/MMC card connector
JTAG and TRACE connectors
power supply
RESET circuit
UEXT connector
Audio IN
Audio OUT
RTC battery
FR-4, 1.5 mm, red soldermask, component print
Dimensions:134.6x101.6mm (5.3 x 4.0")
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ELECTROSTATIC WARNING:
The
LPC1766-STK
board is shipped in protective anti-static packaging. The board
must not be subject to high electrostatic potentials. General practice for working
with static sensitive devices should be applied when working with this board.
BOARD USE REQUIREMENTS:
Cables:
The cable you will need depends on the programmer/debugger you use. If
you use
ARM-JTAG-EW,
you will need USB A-B cable. If you use a software
programmer such as FlashMagic, you will need RS232 cable.
Hardware:
Programmer/Debugger
ARM-JTAG-EW
or other compatible
programming/debugging tool if you work with EW-ARM.
You can use also
ARM-USB-OCD, ARM-USB-TINY, ARM-USB-TINY-H
with
CrossWorks.or OpenOCD.
PROCESSOR FEATURES:
LPC1766-STK
board use ARM 32-bit Cortex™-M3 microcontroller
LPC1766FBD100
from NXP Semiconductors with these features:
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ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A
Memory Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
256 kB on-chip flash programming memory. Enhanced flash memory
accelerator enables high-speed 100 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-
chip bootloader software.
On-chip SRAM includes:
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32 kB of SRAM on the CPU with local code/data bus for high-
performance CPU access.
Two 16 kB SRAM blocks with separate access paths for higher
throughput. These SRAM blocks may be used for Ethernet, USB, and
DMA memory, as well as for general purpose CPU instruction and
data storage.
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Eight channel General Purpose DMA controller (GPDMA) on the AHB
multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-
Digital and Digital-to-Analog converter peripherals, timer match signals, and
for memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB
master. AHB masters include the CPU, General Purpose DMA controller,
Ethernet MAC, and the USB nterface. This interconnect provides
communication with no arbitration delays.
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Split APB bus allows high throughput with few stalls between the CPU and
DMA.
Serial interfaces:
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Ethernet MAC with RMII interface and dedicated DMA controller.
USB 2.0 full-speed device/Host/OTG controller with dedicated DMA
controller and on-chip PHY for device, Host, and OTG functions.
Four UARTs with fractional baud rate generation, internal FIFO, DMA
support, and RS-485 support. One UART has modem control I/O, and
one UART has IrDA support.
CAN 2.0B controller with two channels.
SPI controller with synchronous, serial, full duplex communication
and programmable data length.
Two SSP controllers with FIFO and multi-protocol capabilities. The
SSP interfaces can be used with the GPDMA controller.
Two I2C-bus interfaces supporting fast mode with a data rate of 400
kbits/s with multiple address recognition and monitor mode.
One I2C-bus interface supporting full I2C-bus specification and fast
mode plus with a data rate of 1 Mbit/s with multiple address
recognition and monitor mode.
I2S (Inter-IC Sound) interface for digital audio input or output, with
fractional rate control. The I2S-bus interface can be used with the
GPDMA. The I2S-bus interface supports 3-wire and 4-wire data
transmit and receive as well as master clock input/output.
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Other peripherals:
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70 General Purpose I/O (GPIO) pins with configurable pull-up/down
resistors and a new, configurable open-drain operating mode.
12-bit Analog-to-Digital Converter (ADC) with input multiplexing
among eight pins, conversion rates up to 1 MHz, and multiple result
registers. The 12-bit ADC can be used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion
timer and DMA support.
Four general purpose timers/counters, with a total of eight capture
inputs and ten compare outputs. Each timer block has an external
count input and DMA support.
One motor control PWM with support for three-phase motor control.
Quadrature encoder interface that can monitor one external
quadrature encoder.
One standard PWM/timer block with external count input.
RTC with a separate power domain and dedicated RTC oscillator. The
RTC block includes 64 bytes of battery-powered backup registers.
Watchdog Timer (WDT) resets the microcontroller within a reasonable
amount of time if it enters an erroneous state.
System tick timer, including an external clock input option.
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Repetitive interrupt timer provides programmable and repeating
timed interrupts.
Each peripheral has its own clock divider for further power savings.
Standard JTAG test/debug interface for compatibility with existing tools.
Serial Wire Debug and Serial Wire Trace Port options.
Emulation trace module enables non-intrusive, high-speed real-time tracing of
instruction execution.
Integrated PMU (Power Management Unit) automatically adjusts internal
regulators to minimize power consumption during Sleep, Deep sleep, Power-
down, and Deep power-down modes.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-
down.
Single 3.3 V power supply (2.4 V to 3.6 V).
Four external interrupt inputs configurable as edge/level sensitive. All pins on
PORT0 and PORT2 can be used as edge sensitive interrupt sources.
Non-maskable Interrupt (NMI) input.
Clock output function that can reflect the main oscillator clock, IRC clock, RTC
clock, CPU clock, and the USB clock.
The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake
up from any priority interrupt that can occur while the clocks are stopped in
deep sleep, Power-down, and Deep power-down modes.
Processor wake-up from Power-down mode via interrupts from various
peripherals.
Brownout detect with separate threshold for interrupt and forced reset.
Power-On Reset (POR).
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be
used as a system clock.
PLL allows CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
USB PLL for added flexibility.
Code Read Protection (CRP) with different security levels.
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电源技术
