LS842
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
The LS842 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LS842 features a 25-
mV offset and 40-µV/°C drift.
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
FEATURES
LOW DRIFT
| V
GS1‐2
/ T| ≤40µV/°C
LOW LEAKAGE
I
G
= 10pA TYP.
LOW NOISE
e
n
= 8nV/√Hz TYP.
LOW OFFSET VOLTAGE
| V
GS1‐2
| ≤25mV
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
‐65°C to +150°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐V
GSS
Gate Voltage to Drain or Source
60V
‐V
DSO
Drain to Source Voltage
60V
‐I
G(f)
Gate Forward Current
50mA
Maximum Power Dissipation
Device Dissipation @ Free Air – Total 400mW @ +125°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V
GS1‐2
/ T| max.
DRIFT VS.
40
µV/°C V
DG
=20V, I
D
=200µA
TEMPERATURE
T
A
=‐55°C to +125°C
| V
GS1‐2
| max.
OFFSET VOLTAGE
25
mV
V
DG
=20V, I
D=
200µA
TYP.
60
‐‐
‐‐
‐‐
0.6
2
1
2
‐‐
10
‐‐
5
‐‐
‐‐
0.1
0.01
100
75
‐‐
‐‐
‐‐
4
1.2
0.1
MAX.
‐‐
‐‐
4000
1000
3
5
5
4.5
4
50
50
‐‐
100
10
1
0.1
‐‐
‐‐
0.5
10
15
10
5
‐‐
UNITS
V
V
µmho
µmho
%
mA
%
V
V
pA
nA
pA
pA
µmho
µmho
µmho
dB
CONDITIONS
V
DS
= 0 I
D
=1nA
I
G
= 1nA I
D
= 0 I
S
= 0
V
DG
= 20V V
GS
= 0V f = 1kHz
V
DG
= 20V I
D
= 200µA
V
DG
= 20V V
GS
= 0V
V
DS
= 20V I
D
= 1nA
V
DS
=20V I
D
=200µA
V
DG
= 20V I
D
= 200µA
T
A
= +125°C
V
DG
= 10V I
D
= 200µA
V
DG
= 20V , V
DS
=0
V
DG
= 20V V
GS
= 0V
V
DG
= 20V I
D
= 200µA
LS842 Applications:
Wideband Differential Amps
High-Speed,Temp-Compensated Single-
Ended Input Amps
High-Speed Comparators
Impedance Converters and vibrations
detectors.
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BV
GSS
Breakdown Voltage
60
BV
GGO
Gate‐To‐Gate Breakdown
60
TRANSCONDUCTANCE
Y
fSS
Full Conduction
1000
Y
fS
Typical Operation
500
|Y
FS1‐2
/ Y
FS
|
Mismatch
‐‐
DRAIN CURRENT
I
DSS
Full Conduction
0.5
|I
DSS1‐2
/ I
DSS
|
Mismatch at Full Conduction
‐‐
GATE VOLTAGE
V
GS
(off) or V
p
Pinchoff voltage
1
V
GS
(on)
Operating Range
0.5
GATE CURRENT
‐I
G
max.
Operating
‐‐
‐I
G
max.
High Temperature
‐‐
‐I
G
max.
Reduced V
DG
‐‐
‐I
GSS
max.
At Full Conduction
‐‐
OUTPUT CONDUCTANCE
Y
OSS
Full Conduction
‐‐
Y
OS
Operating
‐‐
|Y
OS1‐2
|
Differential
‐‐
COMMON MODE REJECTION
CMR
‐20 log | V
GS1‐2
/ V
DS
|
‐‐
‐20 log | V
GS1‐2
/ V
DS
|
‐‐
NOISE
NF
Figure
‐‐
e
n
Voltage
‐‐
‐‐
CAPACITANCE
C
ISS
Input
‐‐
C
RSS
Reverse Transfer
‐‐
C
DD
Drain‐to‐Drain
‐‐
Click To Buy
dB
nV/√Hz
pF
∆V
DS
= 10 to 20V I
D
=200µA
∆V
DS
= 5 to 10V I
D
=200µA
V
DS
= 20V V
GS
= 0V R
G
= 10MΩ
f= 100Hz NBW= 6Hz
V
DS
=20V I
D
=200µA f=1KHz NBW=1Hz
V
DS
=20V I
D
=200µA f=10Hz NBW=1Hz
V
DS
= 20V, I
D
=200µA
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
PDIP & SOIC (Top View)
Available Packages:
LS842 / LS842 in PDIP & SOIC
LS842 / LS842 available as bare die
Please contact
Micross
for full package and die dimensions
Tel: +44 1603 788967
Email:
chipcomponents@micross.com
Web:
http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
