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However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
DICE/DWF SPECIFICATION
LT1962
DICE/DWF ELECTRICAL TEST LIMITS
PARAMETER
ADJ Pin Voltage (Notes 4, 5)
Line Regulation
Load Regulation
Dropout Voltage (Notes 6, 7, 12)
V
IN
= V
OUT(NOMINAL)
GND Pin Current (Notes 6, 8)
V
IN
= 2.3V
CONDITIONS
V
IN
= 2V, I
LOAD
= 1mA
ΔV
IN
= 2V to 20V, I
LOAD
= 1mA (Note 4)
V
IN
= 2.3V,
ΔI
LOAD
= 1mA to 50mA (Note 4)
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 0mA
I
LOAD
= 1mA
I
LOAD
= 50mA
I
LOAD
= 100mA
(Notes 4, 9)
V
OUT
= Off to On
V
OUT
= On to Off
V
SHDN
= 0V
V
SHDN
= 20V
V
IN
= 6V, V
SHDN
= 0V
V
IN
= –20V, V
OUT
= 0V
V
OUT
= 1.22V, V
IN
< 1.22V
0.25
0.5
5
1
1
10
T
A
= 25°C
(Note 3)
MIN
1.208
MAX
1.232
5
5
0.15
0.20
75
120
1.6
3
100
2
UNITS
V
mV
mV
V
V
µA
µA
mA
mA
nA
V
V
µA
µA
µA
mA
µA
ADJ Pin Bias Current
Shutdown Threshold
SHDN Pin Current (Note 10)
Quiescent Current in Shutdown
Input Reverse Leakage Current
Reverse Output Current (Note 11)
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Absolute maximum input to output differential voltage cannot
be achieved with all combinations of rated IN pin and OUT pin voltages.
With the IN pin at 20V, the OUT pin may not be pulled below 0V. The total
measured voltage from in to out can not exceed ±20V.
Note 3:
The LT1962 regulators are tested and specified under pulse load
conditions such that T
J
≈
T
A
. The LT1962 is 100% tested at T
A
= 25°C.
Note 4:
The LT1962 (adjustable version) is tested and specified for these
conditions with the ADJ pin connected to the OUT pin.
Note 5:
Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply
for all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 6:
To satisfy requirements for minimum input voltage, the LT1962
(adjustable version) is tested and specified for these conditions with an
external resistor divider (two 250k resistors) for an output voltage of
2.44V. The external resistor divider will add a 5µA DC load on the output.
Note 7:
Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
output voltage will be equal to: V
IN
– V
DROPOUT
.
Note 8:
GND pin current is tested with V
IN
= 2.3V and a current source
load. This means the device is tested while operating close to its dropout
region. This is the worst-case GND pin current. The GND pin current will
decrease slightly at higher input voltages.
Note 9:
ADJ pin bias current flows into the ADJ pin.
Note 10:
SHDN pin current flows into the SHDN pin. This current is
included in the specification for GND pin current.
Note 11:
Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current flows into the OUT
pin and out the GND pin.
Note 12:
For the LT1962, dropout voltage will be limited by the minimum
input voltage specification under some output voltage/load conditions.
See the curve of Minimum Input Voltage in the Typical Performance
Characteristics in the LT1962 data sheet.
Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus
packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information
on dice performance and lot qualifications via lot sampling test procedures.
Dice data sheet subject to change. Please consult factory for current revision in production.
