LTC1421/LTC1421-2.5
Hot Swap Controller
FEATURES
s
s
s
s
s
s
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DESCRIPTION
The LTC
®
1421/LTC1421-2.5 are Hot Swap
TM
controllers
that allow a board to be safely inserted and removed from a
live backplane. Using external N-channel pass transistors,
the board supply voltages can be ramped up at a program-
mable rate. Two high side switch drivers control the N-
channel gates for supply voltages ranging from 3V to 12V.
A programmable electronic circuit breaker protects against
shorts. Warning signals indicate that the circuit breaker
has tripped, a power failure has occurred or that the switch
drivers are turned off. The reset output can be used to
generate a system reset when the power cycles or a fault
occurs. The two connect inputs can be used with stag-
gered connector pins to indicate board insertion or re-
moval. The power-on reset input can be used to cycle the
board power or clear the circuit breaker.
The trip point of the ground sense comparator is set at
0.1V for LTC1421 and 2.5V for LTC1421-2.5.
Allows Safe Board Insertion and Removal from a
Live Backplane
System Reset and Power Good Control Outputs
Programmable Electronic Circuit Breaker
User Programmable Supply Voltage Power-Up Rate
High Side Driver for Two External N-Channels
Controls Supply Voltages from 3V to 12V
Connection Inputs Detect Board Insertion or Removal
Undervoltage Lockout
Power-On Reset Input
APPLICATIONS
s
s
Hot Board Insertion
Electronic Circuit Breaker
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
The LTC1421/LTC1421-2.5 are available in 24-pin SO and
SSOP packages.
TYPICAL APPLICATION
Q3
1/2 Si4936DY
C3
0.47µF
V
EE
V
DD
R1
0.005Ω
V
CC
STAGGERED CONNECTOR
Q2
R2
0.025Ω 1/2 Si4936DY
Q1
MTB50N06E
D1
R3
1k
23
22
21
20
19
18
17
16
10
9
14
13
8
11
15
6
7
V
CCLO
SETLO GATELO V
OUTLO
V
CCHI
2
CON2
24
AUXV
CC
C1
1µF
4
FAULT
SETHI GATEHI V
OUTHI
RAMP
CPON
COMP
–
COMP
+
REF
FB
COMPOUT
PWRGD
RESET
C2
0.1µF
R5
16k
5%
R6
20k
1%
1µF
LTC1421
R7
7.15k
1%
µP
I/O
I/O
RESET
FAULT
POR
3
POR
1
CON1
GND
12
DISABLE
5
1
BEA V
CC
13
BEB
12
GND
QS3384
QuickSwitch
®
GND
DATA BUS
1421 TA01
DATA
BUS
QuickSwitch IS A REGISTERED TRADEMARK
OF QUALITY SEMICONDUCTOR CORPORATION.
BACKPLANE
PC BOARD
+
R4
20k
5%
U
U
U
C5
220µF
V
EE
– 12V
1A
V
DD
12V
1A
V
CC
5V
5A
+
+
C3
220µF
C4
220µF
1
LTC1421/LTC1421-2.5
ABSOLUTE
MAXIMUM
RATINGS
(Note 1)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CON1
CON2
POR
FAULT
DISABLE
PWRGD
RESET
REF
CPON
1
2
3
4
5
6
7
8
9
24 AUXV
CC
23 V
CCLO
22 SETLO
21 GATELO
20 V
OUTLO
19 V
CCHI
18 SETHI
17 GATEHI
16 V
OUTHI
15 COMPOUT
14 COMP
–
13 COMP
+
Supply Voltage (V
CCLO
, V
CCHI
, AUXV
CC
) .............. 13.2V
Input Voltage (Analog Pins) ..... – 0.3V to (V
CCHI
+ 0.3V)
Input Voltage (Digital Pins) ................... – 0.3V to 13.2V
Output Voltage (Digital Pins) .. – 0.3V to (V
CCLO
+ 0.3V)
Output Voltage (CPON) ......... – 13.2V to (V
CCLO
+ 0.3V)
Output Voltage (V
OUTLO
, V
OUTHI
) ........... – 0.3V to 13.2V
Output Voltage (GATELO, GATEHI) ........... – 0.3V to 20V
Operating Temperature Range .................... 0°C to 70°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
LTC1421CG
LTC1421CSW
LTC1421-2.5CG
LTC1421-2.5CSW
RAMP 10
FB 11
GND 12
G PACKAGE
24-LEAD PLASTIC SSOP
SW PACKAGE
24-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 100°C/W (G)
T
JMAX
= 125°C,
θ
JA
= 85°C/W (SW)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL
I
CCLO
I
CCHI
V
LKO
V
LKH
V
REF
∆V
LNR
∆V
LDR
I
RSC
V
COF
V
CPSR
V
CHST
V
RST
PARAMETER
V
CCLO
Supply Current
V
CCHI
Supply Current
Undervoltage Lockout
Undervoltage Lockout Hysteresis
Reference Output Voltage
Reference Line Regulation
Reference Load Regulation
Reference Short-Circuit Current
Comparator Offset Voltage
Comparator Power Supply Rejection
Comparator Hysteresis
Reset Voltage Threshold (V
OUTLO
)
DC Characteristics
V
CCHI
= 12V, V
CCLO
= 5V, T
A
= 25°C unless otherwise noted (Note 2).
MIN
q
q
CONDITIONS
CON1 = CON2 = GND, POR = V
CCLO
CON1 = CON2 = GND, POR = V
CCLO
V
CCLO
and V
CCHI
V
CCLO
and V
CCHI
No Load
3V
≤
V
CCLO
≤
12V, No Load
I
O
=
0mA to – 5mA, Sourcing Only
V
REF
= 0V
0V
≤
V
CM
≤
(V
CCLO
−
1.3V)
0V
≤
V
CM
≤
(V
CCLO
−
1.3V), 3V
≤
V
CCLO
≤
12V
0V
≤
V
CM
≤
(V
CCLO
−
1.3V)
FB = V
OUTLO
FB = Floating
FB = GND
FB = V
OUTLO
FB = Floating
FB = GND
0V
≤
V
FB
≤
V
CCLO
V
CB
= (V
CCLO
– V
SETLO
) or V
CB
= (V
CCHI
– V
SETHI
)
LTC1421 (Note 3)
LTC1421-2.5 (Note 4)
q
q
q
q
q
q
q
q
q
TYP
1.5
0.6
MAX
3
1
2.60
1.244
8
3
±10
1
UNITS
mA
mA
V
mV
V
mV
mV
mA
mV
mV/V
mV
V
V
V
mV
mV
mV
kΩ
2.28
1.220
2.45
100
1.232
4
1
– 45
7
2.80
4.50
5.75
2.90
4.65
5.88
7
12
15
95
40
50
0.1
2.5
60
3.00
4.75
6.01
V
RHST
Reset Threshold Hysteresis (V
OUTLO
)
R
FB
V
CB
V
TRIP
FB Pin Input Resistance
Circuit Breaker Trip Voltage
Output Voltage for Re-Power-Up
2
U
mV
V
V
W
U
U
W W
W
LTC1421/LTC1421-2.5
ELECTRICAL CHARACTERISTICS
SYMBOL
I
RAMP
I
CP
∆V
GATEHI
V
AUXVCC
V
IL
V
IH
I
IN
V
OL
PARAMETER
RAMP Pin Output Current
Charge Pump Output Current
GATEHI N-Channel Gate Drive
Auxiliary V
CC
Output Voltage
Input Low Voltage
Input High Voltage
Input Current
Output Low Voltage
V
CCHI
= 12V, V
CCLO
= 5V, T
A
= 25°C unless otherwise noted (Note 2).
MIN
q
CONDITIONS
Charge Pump On, V
RAMP
=
0.4V
Charge Pump On, GATEHI = 0V
GATELO = 0V
V
GATEHI
−
V
OUTHI
V
GATELO
−
V
OUTLO
V
CCLO
= 5V, Unloaded
CON1, CON2, POR
CON1, CON2, POR
CON1, CON2, POR = GND
RESET, COMPOUT, PWRGD, DISABLE, FAULT,
I
O
= 3mA
CPON, I
O
= 3mA
DISABLE, I
O
= – 3mA
CPON, I
O
= – 1mA
RESET, PWRGD, FAULT = GND
Figure 1, C
L
= 15pF
Figure 1, R
L
= 10k to V
CCLO
, C
L
= 15pF
q
q
q
q
q
q
q
q
q
TYP
17
– 600
– 300
MAX
23
UNITS
µA
µA
µA
11
6
10
4.5
16
16
0.8
V
V
V
V
V
µA
V
V
V
V
∆V
GATELO
GATELO N-Channel Gate Drive
2
– 30
– 60
– 90
0.4
1.45
4
3.4
– 15
15
160
140
160
140
15
20
200
200
200
200
20
32
50
50
20
20
20
30
240
280
240
280
30
V
OH
I
PU
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
9
t
10
t
11
t
CHL
t
CLH
Output High Voltage
Logic Output Pull-Up Current
CON1 or CON2↓ to CPON↑
PWRGD↑ to RESET↑
PWRGD↑ to DISABLE↓
POR↓ to CPON↓
PWRGD↓ to RESET↓
POR↑ to CPON↑
CON1 or CON2↑ to CPON↓
Short-Circuit Detect to FAULT↓
Short-Circuit Detect to CPON↓
POR↑ to FAULT↑
Comparator High to Low
Comparator Low to High
µA
ms
ms
ms
ms
ms
ms
µs
ns
ns
µs
µs
ns
0.5
1.5
µs
µs
AC CHARACTERISTICS
Figure 1, C
L
= 15pF
q
Figure 1, C
L
= 15pF
Figure 1, R
L
= 10k to V
CCLO
, C
L
= 15pF
Figure 1, C
L
= 15pF
Figure 1, C
L
= 15pF
Figure 1, R
L
= 10k to V
CCLO
, C
L
= 15pF
V
CCLO
– SETLO = 0mV to 100mV
Figure 2, C
L
= 15pF
V
CCLO
– SETLO = 0mV to 100mV
Figure 2, R
L
= 10k to V
CCLO
, C
L
= 15pF
COMP
–
= 1.232V, 10mV Overdrive
R
L
= 10k to V
CCLO
, C
L
= 15pF
COMP
–
= 1.232V, 10mV Overdrive
R
L
= 10k to V
CCLO
, C
L
= 15pF
q
q
q
0.25
1
The
q
denotes specifications which apply over the full operating temperature
range.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All currents into device pins are positive; all currents out of device
pins are negative. All voltages are reference to ground unless otherwise
specified.
Note 3:
After power-on reset, the V
OUTLO
and V
OUTHI
have to drop below the
V
TRIP
point before the charge pump is restarted.
Note 4:
After power-on reset, the V
OUTLO
has to drop below the V
TRIP
point
before the charge pump is restarted.
3
LTC1421/LTC1421-2.5
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Voltage vs
Temperature
1.238
1.236
REFERENCE VOLTAGE (V)
1.234
1.232
1.230
1.228
1.226
1.224
– 50 – 25
V
CCLO
= 5V
V
CCHI
= 12V
24
23
GATE VOLTAGE (V)
22
GATEHI
21
20
19
GATELO
18
17
– 50 – 25
V
CCLO
= 5V
V
CCHI
= 12V
REFERENCE VOLTAGE (V)
50
25
75
0
TEMPERATURE (°C)
GATELO Voltage vs V
CCLO
Voltage
26
24
GATELO VOLTAGE (V)
22
20
18
16
14
12
0
2
8
6
10
4
V
CCLO
VOLTAGE (V)
12
14
GATEHI VOLTAGE (V)
V
CCHI
= 12V
26
24
22
20
18
16
14
12
I
CCLO
SUPPLY CURRENT (µA)
I
CCHI
Supply Current
vs Temperature
555
550
I
CCHI
SUPPLY CURRENT (µA)
545
V
CCLO
= 5V
V
CCHI
= 12V
600
500
400
300
VOLTAGE (mV)
540
535
530
525
520
– 50 – 25
COMPOUT
PWRGD
RESET
FAULT
CPON VOLTAGE (V)
50
25
75
0
TEMPERATURE (°C)
4
U W
100
1421 G01
1421 G04
Gate Voltage vs Temperature
1.245
Reference Voltage
vs Source Current
V
CCLO
= 5V
V
CCHI
= 12V
1.240
1.235
1.230
1.225
125
50
25
75
0
TEMPERATURE (°C)
100
125
1.220
0
2
6
8
4
SOURCE CURRENT (mA)
10
1421 G03
1421 G02
GATEHI Voltage vs V
CCHI
Voltage
V
CCLO
= 5V
1500
I
CCLO
Supply Current
vs Temperature
V
CCLO
= 5V
V
CCHI
= 12V
1400
1300
0
2
8
6
10
4
V
CCHI
VOLTAGE (V)
12
14
1200
– 50 – 25
50
25
75
0
TEMPERATURE (°C)
100
125
1421 G05
1421 G06
V
OL
vs I
SINK
2.5
V
CCLO
= 5V
V
CCHI
= 12V
2.0
CPON Voltage vs Sink Current
(Charge Pump Off)
V
CCLO
= 5V
V
CCHI
= 12V
1.5
1.0
200
100
0
0
2
4
6
SINK CURRENT (mA)
8
10
1421 G08
0.5
100
125
0
0
0.5
1.0
1.5
2.0
SINK CURRENT (mA)
2.5
3.0
1421 G09
1421 G07
LTC1421/LTC1421-2.5
TYPICAL PERFORMANCE CHARACTERISTICS
CPON Voltage vs Source Current
(Charge Pump On)
5
V
CCLO
= 5V
V
CCHI
= 12V
4
CPON VOLTAGE (V)
I
CCLO
SUPPLY CURRENT (mA)
7
V
CCHI
= 12V
6
5
4
3
2
1
0
0
– 0.5
– 1.0 – 1.5 – 2.0 – 2.5
SOURCE CURRENT (mA)
– 3.0
0
2
8
6
10
4
V
CCLO
VOLTAGE (V)
12
14
3
2
1
0
PIN FUNCTIONS
CON1 (Pin 1):
TTL Level Input with a Pull-Up to V
CCLO
.
Together with CON2, it is used to indicate board connec-
tion. The pin must be tied to ground on the host side of the
connector. When using staggered connector pins, CON1
and CON2 must be the shortest and must be placed at
opposite corners of the connector. Board insertion is
assumed after CON1 and CON2 are both held low for 20ms
after power-up.
CON2 (Pin 2):
TTL Level Input with a Pull-Up to V
CCLO
.
Together with CON1 it is used to indicate board connec-
tion.
POR (Pin 3):
TTL Level Input with a Pull-Up to V
CCLO
.
When the pin is pulled low for at least 20ms, a hard reset
is generated. Both V
OUTLO
and V
OUTHI
will turn off at a
controlled rate. A power-up sequence will not start until
the POR pin is pulled high. If POR is pulled high before
V
OUTLO
and V
OUTHI
are fully discharged, a power-up
sequence will not begin until the voltage at V
OUTLO
and
V
OUTHI
are below V
TRIP
. The electronic circuit breaker will
be reset by pulling POR low.
FAULT (Pin 4):
Open Drain Output to GND with a Weak
Pull-Up to V
CCLO
. The pin is pulled low when an overcur-
rent fault is detected at V
OUTLO
or V
OUTHI
.
DISABLE (Pin 5):
CMOS Output. The signal is used to
disable the board’s data bus during insertion or removal.
PWRGD (Pin 6):
Open Drain Output to GND with a Weak
Pull-Up to V
CCLO
. The pin is pulled low immediately after
V
OUTLO
falls below its reset threshold voltage. The pin is
pulled high immediately after V
OUTLO
rises above its reset
threshold voltage.
RESET (Pin 7):
Open Drain Output to GND with a Weak
Pull-Up to V
CCLO
. The pin is pulled low when a reset
condition is detected. A reset will be generated when any
of the following conditions are met: Either CON1 or CON2
is high, POR is pulled low, V
CCLO
or V
CCHI
are below their
respective undervoltage lockout thresholds, PWRGD goes
low or an overcurrent fault is detected at V
OUTLO
or
V
OUTHI
. RESET will go high 200ms after PWRGD goes
high. On power failure, RESET will go low 32µs after
PWRGD goes low.
REF (Pin 8):
The Reference Voltage Output. V
OUT
= 1.232V
±1%.
The reference can source up to 5mA of current. A
1µF bypass capacitor is recommended.
CPON (Pin 9):
CMOS Output That Can Be Pulled Below
Ground. CPON is pulled high when the internal charge
pumps for GATELO and GATEHI are turned on. CPON is
pulled low when the charge pumps are turned off. The pin
can be used to control an external MOSFET for a – 5V to
– 12V supply.
U W
I
CCLO
Supply Current
vs V
CCLO
Voltage
1421 G10
1421 G11
U
U
U
5
