Final Electrical Specifications
LTC1642
Hot Swap Controller
May 1999
FEATURES
s
s
DESCRIPTIO
s
s
s
s
s
s
s
s
Single Channel Positive NFET Driver
Programmable Undervoltage and Overvoltage
Protection
Foldback Current Limit
Adjustable Current Limit Time-Out
Latch Off or Automatic Retry on Current Fault
Driver for SCR Crowbar on Overvoltage
Programmable Reset Timer
Reference Output with Uncommitted Comparator
V
CC
: 2.97V to 16.5V Normal Operation, Protected
Against Surges to 33V.
16-Pin SSOP Package
The LTC
®
1642 is a 16-pin Hot Swap
TM
controller that
allows a board to be safely inserted and removed from a
live backplane. Using an external N-channel pass transis-
tor, the board supply voltage can be ramped up at a
programmable rate. A high side switch driver controls the
N-channel gate for supply voltages ranging from 2.97V to
16.5V.
The SENSE pin allows foldback limiting of the load current,
with circuit breaker action after a programmable delay
time. The delay allows the part to power-up in current
limit. The CRWBR output can be used to trigger an SCR
for crowbar load protection after a programmable delay if
the input supply exceeds a programmable voltage. The
RESET output can be used to generate a system reset with
programmable delay when the supply voltage falls below
a programmable voltage. The ON pin can be used to cycle
the board power. The LTC1642 is available in the 16-pin
SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
APPLICATIO S
s
s
Hot Board Insertion
Electronic Circuit Breaker
TYPICAL APPLICATIO
12V
R5
110k
1%
LATCH OFF: FLOAT FAULT
AUTOMATIC RETRY: TIE FAULT TO ON
R1
0.010Ω
5%
C7
0.1µF
Q1
FDR9410A
R2
100Ω
5%
16
15
SENSE
14
GATE
R8
330Ω
5%
C1
0.047µF
RESET
5
7
1
12
Q2
2N2222
Q3
MCR
12DC
V
CC
10
UNDERVOLTAGE = 10.8V
R6
2.87k
1%
OVERVOLTAGE = 13.2V
R7
11.3k
1%
D1
1N4148
4
6
9
COMPOUT
ON
FAULT
OV
LTC1642
FB
CRWBR
COMP
–
11
COMP
+
REF
GND
8
BRK TMR
2
C3
0.33µF
13
RST TMR
C5
3
C2 0.1µF
0.33µF
RESET TIME = 200ms
CURRENT LIMIT TIME = 20ms
CROWBAR TIME = 90µs
C6
0.01µF
R9 REQUIRED ONLY WITH SENSITIVE GATE SCRs,
NOT NEEDED WITH MCR12
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
+
12V
AT 2.5A
C
LOAD
R3
107k
1%
POWER-GOOD = 11.4V
R9
220Ω
5%
R4
13k
1%
1642 TA01
U
U
1
LTC1642
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CRWBR 1
BRK TMR 2
RST TMR 3
ON 4
RESET 5
FAULT 6
FB 7
GND 8
16 V
CC
15 SENSE
14 GATE
13 REF
12 COMP
–
11 COMP
+
10 COMPOUT
9
OV
Supply Voltage (V
CC
) .................................– 0.3V to 33V
SENSE Pin ................................... – 0.3V to (V
CC
+ 0.3V)
GATE Pin ...................................................– 0.3V to 27V
All Other Pins ..........................................– 0.3V to 16.5V
Operating Temperature Range
LTC1642C ............................................... 0°C to 70°C
LTC1642I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1642CGN
LTC1642IGN
GN PACKAGE
16-LEAD PLASTIC SSOP
T
JMAX
= 150°C,
θ
JA
= 130°C/W
Consult factory for Military grade parts.
DC ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C.
V
CC
= 5V unless otherwise specified.
SYMBOL
I
CC
V
LKHI
V
LKLO
V
LKHYST
V
CC
V
FB
∆V
FB
V
FBHST
V
OV
∆V
OV
V
OVHYST
V
RST
∆V
RST
I
RST
V
BRK
∆V
BRK
I
BRK
V
CR
∆V
CR
I
CR
PARAMETER
V
CC
Supply Current
V
CC
Undervoltage Lockout (Low to High)
V
CC
Undervoltage Lockout (High to Low)
V
CC
Undervoltage Lockout Hysteresis
Operating Voltage Range
FB Pin Voltage Threshold (FB Falling)
FB Pin Threshold Line Regulation
FB Pin Voltage Threshold Hysteresis
OV Pin Voltage Threshold (OV Rising)
OV Pin Threshold Line Regulation
OV Pin Voltage Theshold Hysteresis
RST TMR Pin Voltage Threshold (RST TMR Rising)
RST TMR Pin Threshold Line Regulation
RST TMR Pin Current
BRK TMR Pin Voltage Threshold (BRK TMR Rising)
BRK TMR Pin Threshold Line Regulation
BRK TMR Pin Current
CRWBR Pin Voltage Theshold
CRWBR Pin Threshold Line Regulation
CRWBR Pin Current
2.97V
≤
V
CC
≤
16.5V
CRWBR On, V
CRWBR
= 0V
CRWBR On, V
CRWBR
= 2.1V
CRWBR Off, V
CRWBR
= 1.5V
2.97V
≤
V
CC
≤
16.5V
Timer On
Timer Off, V
BRKTMR
= 1.5V
2.97V
≤
V
CC
≤
16.5V
Timer On
Timer Off, V
RSTTMR
= 1.5V
q
q
q
q
q
q
q
q
q
q
q
q
CONDITIONS
ON = V
CC
q
q
q
MIN
2.55
2.35
2.97
1.208
TYP
1.25
2.73
2.50
230
MAX
3.0
2.95
2.80
16.5
UNITS
mA
V
V
mV
V
V
mV
mV
V
mV
mV
V
mV
µA
mA
V
mV
µA
mA
mV
mV
µA
µA
mA
1.220
5
3
1.232
15
1.232
15
1.250
15
–1.5
1.250
15
–15
425
15
– 30
–1000
2.97V
≤
V
CC
≤
16.5V
q
1.208
1.220
5
3
2.97V
≤
V
CC
≤
16.5V
q
1.200
– 2.5
1.200
– 30
375
– 60
1.220
5
–2.0
10
1.220
5
–20
10
410
4
– 45
–1500
2.3
2
U
W
U
U
W W
W
LTC1642
DC ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C.
V
CC
= 5V unless otherwise specified.
SYMBOL
V
CB
I
CP
∆V
GATE
PARAMETER
Circuit Breaker Trip Voltage
GATE Pin Output Current
External N-Channel Gate Drive
CONDITIONS
V
CB
= (V
CC
– V
SENSE
), V
FB
= GND
V
CB
= (V
CC
– V
SENSE
), V
FB
= 1V
Charge Pump On, V
GATE
= GND
Charge Pump Off, V
GATE
= 5V
V
GATE
– V
CC,
V
CC
= 3V
V
GATE
– V
CC,
V
CC
= 5V
V
GATE
– V
CC,
V
CC
= 15V
q
q
q
q
q
q
MIN
15
45
– 30
4.5
10
4.5
1.30
q
TYP
25
52.5
– 25
10
5.9
11.5
8.5
1.34
1.22
110
MAX
36
60
– 20
8.0
14
18
1.38
1.26
0.4
UNITS
mV
mV
µA
mA
V
V
V
V
V
mV
V
µA
V
mV
mV
mA
mV
mV
V
ONHI
V
ONLO
V
ONHYST
V
OL
I
PU
V
REF
∆V
LNR
∆V
LDR
I
RSC
V
COS
V
CHYST
ON Pin Threshold (Low to High)
ON Pin Threshold (High to Low)
ON Pin Hysteresis
Output Low Voltage
Logic Output Pull-Up Current
Reference Output Voltage
Reference Line Regulation
Reference Load Regulation
Reference Short-Circuit Current
Comparator Offset Voltage
Comparator Hysteresis
RESET, FAULT, COMPOUT I
O
= 1.5mA
RESET, FAULT = GND
No Load
2.97V
≤
V
CC
≤
16.5V, No Load
I
O
= 0mA to –1mA, Sourcing Only
V
REF
= 0V
V
CM
= V
REF
V
CM
= V
REF
q
q
q
q
q
1.20
– 15
1.208
1.220
5
2.5
4.5
±10
3
1.232
15
7.5
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
PI FU CTIO S
CRWBR (Pin 1):
Combination Overvoltage Timer and
Crowbar Circuit Trigger. The timer sets the overvoltage
time needed to trigger the crowbar circuit. To use the timer
connect a capacitor C to ground; the trigger time is
9ms•C(µF). When the timer is off an internal N-channel
pulls the pin to ground. The timer is started when the OV
comparator trips. A 45µA current source is connected
from V
CC
to the CRWBR pin, and the voltage increases at
a rate of 45/C(µF) Volts/second. When the voltage reaches
410mV the current sourced by the pin increases to 1.5mA.
Boost this current with an NPN emitter follower to trigger
a crowbar SCR.
BRK TMR (Pin 2):
Analog Timer which Limits the Time the
Part Remains In Current Limit. To use the timer connect a
capacitor from BRK TMR to ground. BRK TMR is pulled to
ground until the sense resistor current reaches its limit,
when the pin begins sourcing 20µA and the pin voltage
increases at a rate of 20/C(µF) Volts/second. When the pin
reaches 1.23V the GATE pin is pulled to ground and the
FAULT output is asserted until the chip is reset. To allow
the part to remain in current limit indefinitely ground BRK
TMR.
RST TMR (Pin 3):
Analog System Timer. To use the timer
connect a capacitor from RST TMR to ground. This timer
sets the delay from the ON pin going high to the start of the
GATE pin’s ramp; it also sets the delay from output voltage
good, as sensed by the FB pin, to RESET going high. When
the timer is off, an internal N-channel shorts RST TMR to
ground. When the timer is turned on a 2µA current from
V
CC
is connected and the RST TMR pin voltage starts to
ramp up at a rate of 2/C(µF) Volts/second. The timer trips
when the voltage reaches 1.23V.
U
U
U
3
LTC1642
PI FU CTIO S
ON (Pin 4):
Control. When ON is low the GATE pin is
grounded and FAULT goes high. The GATE pin voltage
starts ramping up one RST TMR timing cycle after ON
goes high. Pulsing the ON pin low for at least 2µs also
resets the chip when it latches off after a sustained
overvoltage or current limit. The threshold on a low to high
transition is 1.34V with 110mV of hysteresis.
RESET (Pin 5):
Open Drain Output. RESET is pulled low if
the voltage at the FB pin is below its trip point and goes
high one timing cycle after the FB voltage exceeds its trip
point plus 3mV of hysteresis. RESET has a weak pull-up to
one diode drop below V
CC
; an external resistor can pull the
pin above V
CC
.
FAULT (Pin 6):
Open Drain Output. FAULT is pulled low
when the part latches itself off following a sustained
overvoltage or current limit. It goes high 2µs after the ON
pin goes low. FAULT has a weak pull-up to one diode drop
below V
CC
; an external resistor can pull the pin above V
CC
.
FB (Pin 7):
Noninverting Input to An Analog Comparator;
the inverting input is tied to the 1.23V internal reference.
The FB comparator can be used with an external resistive
divider to monitor the output supply voltage. When the FB
voltage is lower than 1.23V the RESET pin is pulled low.
RESET goes high one system timing cycle after the voltage
at FB exceeds its threshold by 3mV of hysteresis. A low
pass filter at the comparator’s output prevents negative
voltage glitches from triggering a false reset.
GND (Pin 8):
Chip Ground.
OV (Pin 9):
Analog Input Used to Monitor Overvoltages.
When the voltage on OV exceeds its trip point the GATE pin
is pulled low immediately and the CRWBR timer starts. If
OV remains above its trip point (minus 3mV of hysteresis)
long enough for CRWBR to reach its trip point the part
latches off until reset by pulsing the ON pin low; otherwise,
the GATE pin begins ramping up one RST TMR timing
cycle after OV goes below its trip point.
COMPOUT (Pin 10):
Uncommitted Comparator’s Open
Drain Output.
COMP
+
(Pin 11):
Uncommitted Comparator’s Noninvert-
ing Input.
COMP
–
(Pin 12):
Uncommitted Comparator’s Inverting
Input.
REF (Pin 13):
The Reference Voltage Output, 1.232V
±2%.
To ensure stability the pin should be bypassed with
a 0.1µF compensation capacitor. For V
CC
= 5V it can
source 1mA.
GATE (Pin 14):
High Side Gate Drive for the External
N-Channel. An internal charge pump provides at least 4.5V
of gate drive, but can only source 25µA. The pin requires
an external series RC network to ground to compensate
the current limit loop, and to limit the maximum voltage
ramp which is dV/dt (V/s) = 25/C(µF). GATE is immediately
pulled to ground when the overvoltage comparator trips or
the input supply is below the undervoltage lockout trip
point. During current limit the GATE voltage is adjusted to
maintain constant load current until the BRK TMR pin
trips, when the pin is pulled to ground until the chip is
reset.
SENSE (Pin 15):
Current Limit Set. To use the current limit
place a sense resistor in the supply path between V
CC
and
SENSE. Should the drop across the resistor exceed a
threshold voltage the GATE pin is adjusted to maintain a
constant load current and the timer at the BRK TMR pin is
started. To protect the external FET from thermal damage
the circuit breaker trips after the BRK TMR timing cycle. A
foldback feature makes the current limit decrease as the
voltage at FB approaches ground. Figure 3 quantifies the
relationship. To disable the current limit short SENSE to
V
CC
.
V
CC
(Pin 16):
Positive Supply Voltage; between 2.97V and
16.5V in normal operation. An internal undervoltage lock-
out circuit holds the GATE pin at ground until V
CC
exceeds
2.73V. If V
CC
exceeds 16.5V an internal shunt regulator
protects the chip from V
CC
and SENSE pin voltages up to
33V. When the internal shunt regulator is active and the
charge pump is on the GATE pin voltage will usually be low
but this is not guaranteed; use the OV pin to ensure that the
pass device is off. The V
CC
pin also provides a Kelvin
connection to the high side of the SENSE resistor.
4
U
U
U
LTC1642
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When a circuit board is inserted into a live backplane its
supply bypass capacitors can draw large currents from the
backplane power bus as they charge. These currents can
permanently damage connector pins and can glitch the
backplane supply, resetting other boards in the system.
The LTC1642 limits the charging currents drawn by a
board’s capacitors, allowing safe insertion in a live
backplane.
Power Supply Ramping
In the circuit shown in Figure 1 the LTC1642 and the
external N-channel pass transistor Q1 work together to
limit charging currents. When power is first applied to V
CC
the chip holds Q1’s gate at ground. After a programmable
delay a 25µA current source begins to charge the external
capacitor C2, generating a voltage ramp of 25µA/C2 V/s at
the GATE pin. Because Q1 acts as a source follower while
its gate ramps, the current charging the board’s bypass
capacitance C
LOAD
is limited to 25µA•C
LOAD
/C2.
An internal charge pump supplies the 25µA gate current,
ensuring sufficient gate drive to Q1. At 3V V
CC
the mini-
mum gate drive is 4.5V; at 5V V
CC
the minimum is 10V; at
15V V
CC
the minimum is again 4.5V, due to a Zener clamp
from the GATE pin to ground. Resistor R3 limits this
Zener’s transient current during board insertion and re-
moval and protects against high frequency FET oscilla-
tions.
R2
Q1
V
IN
12V
2.5A
C7
0.1µF
R1
10k
4
0.010Ω
16
V
CC
ON
15
SENSE
GATE
14
R4
330Ω
C2
0.047µF
5
FDR9410A
VOLTS
+
R3
100Ω
LTC1642
2
BRK TMR
RST TMR
RESET
GND
8
C4
0.33µF
C1
0.33µF
3
ALL RESISTORS
±5%
UNLESS NOTED
RESET DELAY = 200ms
SHORT-CIRCUIT DURATION = 20ms
Figure 1. Supply Control Circuitry
U
The delay before the GATE pin voltage begins ramping is
determined by the system timer. It comprises an external
capacitor C1 from the RST TMR pin to ground; an internal
2µA current source feeding RST TMR from V
CC
; an internal
comparator, with the positive input tied to RST TMR and
the negative input tied to the 1.23V reference; and an
NMOS pull-down. In standby, the NMOS holds RST TMR
at ground; when the timer starts the NMOS turns off and
the RST TMR voltage ramps up as the current source
charges the capacitor. When RST TMR reaches 1.23V the
timer comparator trips; the GATE voltage begins ramping
and RST TMR returns to ground. The ramp time
∆t
needed
to trip the comparator is :
∆t(ms)
= 615•C1(µF).
V
IN
RST TMR
GATE
SLOPE = 25µA/C(V/s)
V
OUT
TIME
1642 F02
W
U
U
Figure 2. Supply Control Timing
Powering-Up In Current Limit
Ramping the GATE pin voltage
indirectly
limits the charg-
ing current to I = 25µA•C
LOAD
/C2, where C2 is the external
capacitor connected to the GATE and C
LOAD
is the load
capacitance. If the value of C
LOAD
is uncertain, then a
worst-case design can often result in needlessly long
ramp times, and it may be better to limit the charging
current directly.
Current Limiting and Solid-State Circuit Breaker
The board current can be limited by connecting a sense
resistor between the LTC1642’s V
CC
and SENSE pins. An
internal servo loop adjusts the GATE pin voltage such that
Q1 acts as a constant current source if the voltage drop
across the sense resistor reaches a limit. The voltage limit
across the sense resistor increases as the output charges
V
OUT
C
LOAD
1642 F01
5
