首页 > 器件类别 >

LTC1750CFW#TRPBF

1-Channel Single ADC Pipelined 80Msps 14-bit Parallel 48-Pin TSSOP T/R

厂商名称:ADI(亚德诺半导体)

厂商官网:https://www.analog.com

下载文档
器件参数
参数名称
属性值
欧盟限制某些有害物质的使用
Compliant
ECCN (US)
3A991.c.3
Part Status
Active
HTS
8542.39.00.01
Converter Type
General Purpose
Architecture
Pipelined
Resolution
14bit
Number of ADCs
1
Number of Input Channels
1
Sampling Rate
80Msps
Digital Interface Type
Parallel
Input Type
Voltage
Input Signal Type
Single-Ended|Differential
Voltage Reference
External|Internal
Polarity of Input Voltage
Bipolar
Voltage Supply Source
Single
Input Voltage
±0.7V/±1.125V
Minimum Single Supply Voltage (V)
4.75
Typical Single Supply Voltage (V)
5
Maximum Single Supply Voltage (V)
5.25
Typical Power Dissipation (mW)
1450
Maximum Power Dissipation (mW)
1690
Integral Nonlinearity Error
±3LSB
Full Scale Error
3.5%FSR
Signal to Noise Ratio
75.5dB(Typ)
No Missing Codes (bit)
14
Sample and Hold
Yes
Single-Ended Input
Yes
Digital Supply Support
No
Minimum Operating Temperature (°C)
0
Maximum Operating Temperature (°C)
70
系列
Packaging
Tape and Reel
Supplier Temperature Grade
Commercial
Pin Count
48
Standard Package Name
SOP
Supplier Package
TSSOP
Mounting
Surface Mount
Package Height
0.95(Max)
Package Length
12.6(Max)
Package Width
6.2(Max)
PCB changed
48
Lead Shape
Gull-wing
参考设计
展开全部 ↓
文档预览
LTC1750
14-Bit, 80Msps
Wide Bandwidth ADC
DESCRIPTIO
The LTC
®
1750 is an 80Msps, 14-bit A/D converter de-
signed for digitizing wide dynamic range signals up to
frequencies of 500MHz. The input range of the ADC can be
optimized with the on-chip PGA sample-and-hold circuit
and flexible reference circuitry.
The LTC1750 has a highly linear sample-and-hold circuit
with a bandwidth of 500MHz. The SFDR is 82dB with an
input frequency of 250MHz. Ultralow jitter of 0.12ps
RMS
allows undersampling of IF frequencies with minimal
degradation in SNR. DC specs include
±3LSB
INL and no
missing codes.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to any low voltage
DSPs or FIFOs.
The 48-pin TSSOP package with a flow-through pinout
simplifies the board layout.
, LTC and LT are registered trademarks of Linear Technology Corporation.
FEATURES
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
Sample Rate: 80Msps
500MHz Full Power Bandwidth S/H
Direct IF Sampling Up to 500MHz
PGA Front End (2.25V
P-P
or 1.35V
P-P
Input Range)
75.5dB SNR and 90dB SFDR (PGA = 0)
73dB SNR and 90dB SFDR (PGA = 1)
No Missing Codes
Single 5V Supply
Power Dissipation: 1.45W
Two Pin Selectable Reference Values
Two’s Complement or Offset Binary Outputs
Out-of-Range Indicator
Data Ready Output Clock
Pin-for-Pin Family
48-Pin TSSOP Package
APPLICATIO S
s
s
s
s
s
s
s
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
MRI
Tomography
BLOCK DIAGRA
PGA
A
IN+
±1.125V
DIFFERENTIAL
ANALOG INPUT A
IN
SENSE
80Msps, 14-Bit ADC with a 2.25V Differential Input Range
OV
DD
0.1µF
S/H
CIRCUIT
14-BIT
PIPELINED ADC
CORRECTION
LOGIC AND
SHIFT
REGISTER
14
OUTPUT
LATCHES
OF
D13
D0
CLKOUT
0.5V TO 5V
0.1µF
BUFFER
V
DD
RANGE
SELECT
1µF
DIFF AMP
GND
CONTROL LOGIC
1750 BD
V
CM
4.7µF
2V
REF
REFLB
0.1µF
1µF
REFHA
4.7µF
REFLA
REFHB
0.1µF
ENC
ENC
1µF
DIFFERENTIAL
ENCODE INPUT
U
W
U
OGND
1µF
5V
1µF
MSBINV
1750f
1
LTC1750
ABSOLUTE
MAXIMUM
RATINGS
OV
DD
= V
DD
(Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW
SENSE
V
CM
GND
A
IN+
A
IN–
GND
V
DD
V
DD
GND
REFLB
REFHA
GND
GND
REFLA
REFHB
GND
V
DD
V
DD
GND
V
DD
GND
MSBINV
ENC
ENC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FW PACKAGE
48-LEAD PLASTIC TSSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OF
OGND
D13
D12
D11
OV
DD
D10
D9
D8
D7
OGND
GND
GND
D6
D5
D4
OV
DD
D3
D2
D1
D0
OGND
CLKOUT
PGA
Supply Voltage (V
DD
) ............................................. 5.5V
Analog Input Voltage (Note 3) .... – 0.3V to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) ..... – 0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ................. – 0.3V to (V
DD
+ 0.3V)
OGND Voltage ..............................................– 0.3V to 1V
Power Dissipation ............................................ 2000mW
Operating Temperature Range
LTC1750C ............................................... 0°C to 70°C
LTC1750I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1750CFW
LTC1750IFW
T
JMAX
= 150°C,
θ
JA
= 35°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Full-Scale Tempco
Offset Tempco
Input Referred Noise (Transition Noise)
CONDITIONS
The
q
indicates specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
q
(Note 6)
q
(Note 7) External Reference (V
SENSE
= 1.125V, PGA = 0)
External Reference (V
SENSE
= 1.125V, PGA = 0)
Internal Reference
External Reference (V
SENSE
= 1.125V)
V
SENSE
= 1.125V, PGA = 0
MIN
14
–3
–1
–35
–3.5
TYP
±0.75
±0.5
±8
±1
±40
±20
±20
0.92
MAX
3
1.5
35
3.5
UNITS
Bits
LSB
LSB
mV
%FS
ppm/°C
ppm/°C
µV/°C
LSB
RMS
A ALOG I PUT
SYMBOL
V
IN
I
IN
C
IN
t
ACQ
t
AP
t
JITTER
CMRR
The
q
indicates specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
PARAMETER
Analog Input Range (Note 8)
Analog Input Leakage Current
Analog Input Capacitance
Sample-and-Hold Acquisition Time
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
CONDITIONS
4.75V
V
DD
5.25V
0 < A
IN+
, A
IN–
< V
DD
Sample Mode ENC < ENC
Hold Mode ENC > ENC
MIN
q
q
–1
q
1.5V < (A
IN–
= A
IN+
) < 3V
TYP
MAX
±0.7
to
±1.125
1
6.9
2.4
5
6
0
0.12
80
UNITS
V
µA
pF
pF
ns
ns
ps
RMS
dB
1750f
2
U
W
U
U
W W
W
U
U
U
LTC1750
DY A IC ACCURACY
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
SFDR
S/(N + D)
THD
IMD
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
V
CM
Output Voltage
V
CM
Output Tempco
V
CM
Line Regulation
V
CM
Output Resistance
CONDITIONS
I
OUT
= 0
I
OUT
= 0
4.75V
V
DD
5.25V
1mA
≤ I
OUT
 ≤
1mA
U
W U
U
T
A
= 25°C, A
IN
= –1dBFS (Note 5), V
SENSE
= V
DD
CONDITIONS
5MHz Input Signal (PGA = 0)
5MHz Input Signal (PGA = 1)
30MHz Input Signal (PGA = 0)
30MHz Input Signal (PGA = 1)
70MHz Input Signal (PGA = 0)
70MHz Input Signal (PGA = 1)
140MHz Input Signal (PGA = 1)
250MHz Input Signal (PGA = 1)
350MHz Input Signal (PGA = 1)
73
MIN
TYP
75.5
73.0
75.3
72.9
74.6
72.8
72
70.6
69
90
90
80
85
90
95
90
85
80
83
90
95
84
82
74
75.2
72.8
75.1
72.6
74.3
72.4
70
–90
–90
–90
–90
–85
–90
78
– 90
– 90
500
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBc
dBc
MHz
70
Spurious Free Dynamic Range
5MHz Input Signal (PGA = 0)
5MHz Input Signal (PGA = 1)
30MHz Input Signal (PGA = 0) (HD2 and HD3)
30MHz Input Signal (PGA = 0) Other
30MHz Input Signal (PGA = 1)
70MHz Input Signal (PGA = 0)
70MHz Input Signal (PGA = 1) (HD2 and HD3)
70MHz Input Signal (PGA = 1) Other
140MHz Input Signal (PGA = 1)
250MHz Input Signal (PGA = 1)
350MHz Input Signal (PGA = 1)
Signal-to-(Noise + Distortion) Ratio
5MHz Input Signal (PGA = 0)
5MHz Input Signal (PGA = 1)
30MHz Input Signal (PGA = 0)
30MHz Input Signal (PGA = 1)
70MHz Input Signal (PGA = 0)
70MHz Input Signal (PGA = 1)
250MHz Input Signal (PGA = 1)
Total Harmonic Distortion
5MHz Input Signal, First 5 Harmonics (PGA = 0)
5MHz Input Signal, First 5 Harmonics (PGA = 1)
30MHz Input Signal, First 5 Harmonics (PGA = 0)
30MHz Input Signal, First 5 Harmonics (PGA = 1)
70MHz Input Signal, First 5 Harmonics (PGA = 0)
70MHz Input Signal, First 5 Harmonics (PGA = 1)
250MHz Input Signal (PGA = 1)
Intermodulation Distortion
Sample-and-Hold Bandwidth
f
IN1
= 2.52MHz, f
IN2
= 5.2MHz (PGA = 0)
f
IN1
= 2.52MHz, f
IN2
= 5.2MHz (PGA = 1)
R
SOURCE
= 50Ω
U
(Note 5)
MIN
1.95
TYP
2
±30
3
4
MAX
2.05
UNITS
V
ppm/°C
mV/V
1750f
3
LTC1750
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
SOURCE
I
SINK
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Output Source Current
Output Sink Current
CONDITIONS
V
DD
= 5.25V, MSBINV and PGA
V
DD
= 4.75V, MSBINV and PGA
V
IN
= 0V to V
DD
MSBINV and PGA Only
OV
DD
= 4.75V
OV
DD
= 4.75V
V
OUT
= 0V
V
OUT
= 5V
I
O
= –10µA
I
O
= – 200µA
I
O
= 160µA
I
O
= 1.6mA
q
q
q
q
q
The
q
indicates specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
MIN
2.4
0.8
±10
1.5
4.74
4
4.74
0.05
0.1
– 50
50
0.4
TYP
MAX
UNITS
V
V
µA
pF
V
V
V
V
mA
mA
POWER REQUIRE E TS
SYMBOL
V
DD
I
DD
P
DIS
OV
DD
PARAMETER
Positive Supply Voltage
Positive Supply Current
Power Dissipation
Digital Output Supply Voltage
The
q
indicates specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
q
q
0.5
MIN
4.75
290
1.45
TYP
MAX
5.25
338
1.69
V
DD
UNITS
V
mA
W
V
TI I G CHARACTERISTICS
SYMBOL
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
PARAMETER
ENC Period
ENC High
ENC Low
Aperture Delay
ENC to CLKOUT Falling
ENC to CLKOUT Rising
For 80Msps 50% Duty Cycle
ENC to DATA Delay
ENC to DATA Delay (Hold Time)
ENC to DATA Delay (Setup Time)
For 80Msps 50% Duty Cycle
CLKOUT to DATA Delay (Hold Time),
80Msps 50% Duty Cycle
CLKOUT to DATA Delay (Setup Time),
80Msps 50% Duty Cycle
Data Latency
The
q
indicates specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
(Note 9)
(Note 8)
(Note 8)
(Note 8)
C
L
= 10pF (Note 8)
C
L
= 10pF (Note 8)
C
L
= 10pF (Note 8)
C
L
= 10pF (Note 8)
(Note 8)
C
L
= 10pF (Note 8)
C
L
= 10pF (Note 8)
(Note 8)
C
L
= 10pF (Note 8)
q
q
q
5.3
6
2.1
5
q
q
q
7.25
2
1.4
q
1
q
q
q
MIN
12.5
6
6
0
2.4
t
1
+ t
4
8.65
4.9
3.4
t
0
– t
6
7.6
10.5
10.25
7.2
4.7
4
TYP
MAX
2000
1000
1000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycles
4
U W
U
U
UW
1750f
LTC1750
ELECTRICAL CHARACTERISTICS
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to GND (unless otherwise
noted).
Note 3:
When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
DD
without latchup.
Note 4:
When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
>100mA below GND without latchup. These pins are not clamped to V
DD
.
Note 5:
V
DD
= 5V, f
SAMPLE
= 80MHz, differential ENC/ENC = 2V
P-P
80MHz
sine wave, input range =
±1.125V
differential, unless otherwise specified.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7:
Bipolar offset is the offset voltage measured from – 0.5 LSB
when the output code flickers between 00 0000 0000 0000 and 11
1111 1111 1111.
Note 8:
Guaranteed by design, not subject to test.
Note 9:
Recommended operating conditions.
TYPICAL PERFOR A CE CHARACTERISTICS
INL
2.5
2.0
1.5
1.0
1.0
0.8
0.6
AMPLITUDE (dBFS)
ERROR (LSB)
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
0
4096
12288
8192
OUTPUT CODE
16384
1750 G01
ERROR (LSB)
8192 Point FFT, f
IN
= 15.2MHz,
–10dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
0
–10
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
–100
–110
–120
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
AMPLITUDE (dBFS)
U W
1750 G04
DNL
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
4096
12288
8192
OUTPUT CODE
16384
1750 G02
8192 Point FFT, f
IN
= 15.2MHz,
–1dB, PGA = 0
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–120
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
1750 G03
8192 Point FFT, f
IN
= 15.2MHz,
–20dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
8192 Point FFT, f
IN
= 30.2MHz,
–1dB, PGA = 0
–30
–40
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
1750 G05
1750 G06
1750f
5
查看更多>
参数对比
与LTC1750CFW#TRPBF相近的元器件有:LTC1750CFW#PBF、LTC1750IFW#PBF、LTC1750IFW#TRPBF。描述及对比如下:
型号 LTC1750CFW#TRPBF LTC1750CFW#PBF LTC1750IFW#PBF LTC1750IFW#TRPBF
描述 1-Channel Single ADC Pipelined 80Msps 14-bit Parallel 48-Pin TSSOP T/R 1-Channel Single ADC Pipelined 80Msps 14-bit Parallel 48-Pin TSSOP Tube 1-Channel Single ADC Pipelined 80Msps 14-bit Parallel 48-Pin TSSOP Tube 1-Channel Single ADC Pipelined 80Msps 14-bit Parallel 48-Pin TSSOP T/R
欧盟限制某些有害物质的使用 Compliant Compliant Compliant Compliant
ECCN (US) 3A991.c.3 3A991.c.3 3A991.c.3 3A991.c.3
Part Status Active Active Active Active
Converter Type General Purpose General Purpose General Purpose General Purpose
Architecture Pipelined Pipelined Pipelined Pipelined
Resolution 14bit 14bit 14bit 14bit
Number of ADCs 1 1 1 1
Number of Input Channels 1 1 1 1
Sampling Rate 80Msps 80Msps 80Msps 80Msps
Digital Interface Type Parallel Parallel Parallel Parallel
Input Type Voltage Voltage Voltage Voltage
Input Signal Type Single-Ended|Differential Single-Ended|Differential Single-Ended|Differential Single-Ended|Differential
Voltage Reference External|Internal Internal|External Internal|External Internal|External
Polarity of Input Voltage Bipolar Bipolar Bipolar Bipolar
Voltage Supply Source Single Single Single Single
Input Voltage ±0.7V/±1.125V ±0.7V/±1.125V ±0.7V/±1.125V ±0.7V/±1.125V
Minimum Single Supply Voltage (V) 4.75 4.75 4.75 4.75
Typical Single Supply Voltage (V) 5 5 5 5
Maximum Single Supply Voltage (V) 5.25 5.25 5.25 5.25
Typical Power Dissipation (mW) 1450 1450 1450 1450
Maximum Power Dissipation (mW) 1690 1690 1690 1690
Integral Nonlinearity Error ±3LSB ±3LSB ±3LSB ±3LSB
Full Scale Error 3.5%FSR 3.5%FSR 3.5%FSR 3.5%FSR
Signal to Noise Ratio 75.5dB(Typ) 75.5dB(Typ) 75.5dB(Typ) 75.5dB(Typ)
No Missing Codes (bit) 14 14 14 14
Sample and Hold Yes Yes Yes Yes
Single-Ended Input Yes Yes Yes Yes
Digital Supply Support No No No No
Maximum Operating Temperature (°C) 70 70 85 85
系列
Packaging
Tape and Reel Tube Tube Tape and Reel
Supplier Temperature Grade Commercial Commercial Industrial Industrial
Pin Count 48 48 48 48
Standard Package Name SOP SOP SOP SOP
Supplier Package TSSOP TSSOP TSSOP TSSOP
Mounting Surface Mount Surface Mount Surface Mount Surface Mount
Package Height 0.95(Max) 0.95(Max) 0.95(Max) 0.95(Max)
Package Length 12.6(Max) 12.6(Max) 12.6(Max) 12.6(Max)
Package Width 6.2(Max) 6.2(Max) 6.2(Max) 6.2(Max)
PCB changed 48 48 48 48
Lead Shape Gull-wing Gull-wing Gull-wing Gull-wing
热门器件
热门资源推荐
器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
需要登录后才可以下载。
登录取消