simultaneous sampling 12-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 71dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSB
RMS
.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode) or one bit at a time (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer
allows high performance at full speed for a wide range of
clock duty cycles.
2-Channel Simultaneous Sampling ADC
71dB SNR
90dB SFDR
Low Power: 167mW/112mW/94mW Total
83mW/56mW/47mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm
×
6mm) QFN Package
APPLICATIONS
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
V
DD
CH.1
ANALOG
INPUT
CH.2
ANALOG
INPUT
ENCODE
INPUT
1.8V
OV
DD
OUT1A
OUT1B
DATA
SERIALIZER
OUT2A
OUT2B
DATA
CLOCK
OUT
FRAME
GND
OGND
226512 TA01
LTC2265-12, 65Msps,
2-Tone FFT, f
IN
= 70MHz and 75MHz
0
–10
–20
–30
AMPLITUDE (dBFS)
–40
–50
–60
–70
–80
SERIALIZED
LVDS
OUTPUTS
+
S/H
–
+
S/H
–
12-BIT
ADC CORE
12-BIT
ADC CORE
PLL
–90
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
226512 TA02
22654312fb
1
LTC2265-12/
LTC2264-12/LTC2263-12
ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
PIN CONFIGURATION
TOP VIEW
PAR/SER
OUT1A
+
OUT2B
–
OUT1A
–
30 OUT1B
+
29 OUT1B
–
28 DCO
+
27 DCO
–
41
GND
26 OV
DD
25 OGND
24 FR
+
23 FR
–
22 OUT2A
+
21 OUT2A
–
11 12 13 14 15 16 17 18 19 20
V
DD
V
DD
ENC
+
ENC
–
OUT2B
+
CS
SCK
SDI
GND
SENSE
V
REF
GND
GND
SDO
V
DD
A
IN1+
1
A
IN1–
2
V
CM1
3
REFH 4
REFH 5
REFL 6
REFL 7
V
CM2
8
A
IN2+
9
A
IN2–
10
V
DD
Supply Voltages
V
DD
, OV
DD
................................................ –0.3V to 2V
Analog Input Voltage (A
IN +
, A
IN –
, PAR/SER,
SENSE) (Note 3) .......................... –0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTC2265C, 2264C, 2263C ........................ 0°C to 70°C
LTC2265I, 2264I, 2263I .......................–40°C to 85°C
Storage Temperature Range...................–65°C to 150°C
40 39 38 37 36 35 34 33 32 31
UJ PACKAGE
40-LEAD (6mm
×
6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2265CUJ-12#PBF
LTC2265IUJ-12#PBF
LTC2264CUJ-12#PBF
LTC2264IUJ-12#PBF
LTC2263CUJ-12#PBF
LTC2263IUJ-12#PBF
TAPE AND REEL
LTC2265CUJ-12#TRPBF
LTC2265IUJ-12#TRPBF
LTC2264CUJ-12#TRPBF
LTC2264IUJ-12#TRPBF
LTC2263CUJ-12#TRPBF
LTC2263IUJ-12#TRPBF
PART MARKING*
LTC2265UJ-12
LTC2265UJ-12
LTC2264UJ-12
LTC2264UJ-12
LTC2263UJ-12
LTC2263UJ-12
PACKAGE DESCRIPTION
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
22654312fb
2
LTC2265-12/
LTC2264-12/LTC2263-12
CONVERTER CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
l
LTC2265-12
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
External Reference
Internal Reference
External Reference
External Reference
Differential Analog Input
(Note 7)
Internal Reference
External Reference
MIN
12
–1
–0.5
–12
–2.4
±0.3
±0.1
±3
–0.8
–0.8
±20
±30
±10
±0.2
±3
0.32
1
0.5
12
0.6
TYP
MAX
MIN
12
–1
–0.4
–12
–2.4
LTC2264-12
TYP
±0.3
±0.1
±3
–0.8
–0.8
±20
±30
±10
±0.2
±3
0.32
MAX
1
0.4
12
0.6
12
–1
LTC2263-12
MIN
TYP
±0.3
±0.1
±3
–0.8
–0.8
±20
±30
±10
±0.2
±3
0.32
MAX
1
0.5
12
0.6
UNITS
Bits
LSB
LSB
mV
%FS
%FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSB
RMS
Differential Analog Input (Note 6)
l
l
l
l
–0.5
–12
–2.4
ANALOG INPUT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
External Reference Mode
Per Pin, 65Msps
Per Pin, 40Msps
Per Pin, 25Msps
0 < A
IN +
, A
IN –
< V
DD
0 < PAR/SER < V
DD
0.625 < SENSE < 1.3V
l
l
l
l
l
V
CM
– 100mV
l
MIN
TYP
1 to 2
V
CM
1.250
81
50
31
MAX
V
CM
+ 100mV
1.300
UNITS
V
P-P
V
V
µA
µA
µA
Analog Input Range (A
IN +
– A
IN –
)
Analog Input Common Mode (A
IN +
+ A
IN –
)/2
External Voltage Reference Applied to SENSE
Analog Input Common Mode Current
0.625
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
–1
–3
–6
0
0.15
80
1
3
6
µA
µA
µA
ns
ps
RMS
dB
MHz
Figure 6 Test Circuit
800
22654312fb
3
LTC2265-12/
LTC2264-12/LTC2263-12
DYNAMIC ACCURACY
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
LTC2265-12
CONDITIONS
5MHz Input
30MHz Input
70MHz Input
140MHz Input
l
LTC2264-12
MIN
69.7
TYP
70.9
70.8
70.8
70.5
90
90
89
84
90
90
90
90
70.8
70.7
70.6
70.2
–105
MAX
LTC2263-12
MIN
69.4
TYP
70.5
70.5
70.5
70.2
90
90
89
84
90
90
90
90
70.5
70.4
70.3
69.9
–105
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
MIN
69.9
TYP
71
71
70.9
70.6
90
90
89
84
90
90
90
90
70.9
70.9
70.7
70.3
–105
MAX
SFDR
Spurious Free Dynamic Range 5MHz Input
2
nd
or 3
rd
Harmonic
30MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4
th
Harmonic or Higher
30MHz Input
70MHz Input
140MHz Input
l
77
79
79
l
84
85
84
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
10MHz Input
l
69.6
69.6
69.2
Crosstalk
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400µA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600µA < I
OUT
< 1mA
I
OUT
= 0
1.225
CONDITIONS
I
OUT
= 0
MIN
0.5 • V
DD
– 25mV
TYP
0.5 • V
DD
±25
4
1.250
±25
7
0.6
1.275
MAX
0.5 • V
DD
+ 25mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
INTERNAL REFERENCE CHARACTERISTICS
22654312fb
4
LTC2265-12/
LTC2264-12/LTC2263-12
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
Differential Encode Mode (ENC
–
Not Tied to GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
V
IN
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
R
OL
I
OH
C
OUT
V
OD
V
OS
R
TERM
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
= 1.8V
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 8)
Internally Set
Externally Set (Note 8)
ENC
+
, ENC
–
to GND
(See Figure 10)
l
l
l
0.2
1.1
0.2
10
3.5
1.2
1.6
3.6
V
V
V
V
kΩ
pF
V
0.6
V
V
kΩ
pF
V
0.6
V
µA
pF
Ω
10
3
µA
pF
454
250
1.375
1.375
mV
mV
V
V
Ω
10
3
3.6
30
3.5
Single-Ended Encode Mode (ENC
–
Tied to GND)
V
DD
= 1.8V
V
DD
= 1.8V
ENC
+
to GND
(See Figure 11)
l
l
l
1.2
0
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
V
DD
= 1.8V
V
DD
= 1.8V
V
IN
= 0V to 3.6V
l
l
l
1.3
–10
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)
