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Am29LV640MT/B

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not available for designs. For new and current designs,

S29GL064A supersedes Am29LV640MT/B and is the factory-recommended migration path. Please

refer to the S29GL064A datasheet for specifications and ordering information. Availability of this doc-

ument is retained for reference and historical purposes only.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number

26190

Revision

Amendment

Issue Date

February 1, 2007

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29LV640MT/B

64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™

3.0 Volt-only Boot Sector Flash Memory

This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640M T/B and is the factory-recommended migration path.

Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

Single power supply operation

— 3 V for read, erase, and program operations

Manufactured on 0.23 µm MirrorBit process

technology

Secured Silicon Sector region

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

— Can be programmed and locked at the factory or by

the customer

Flexible sector architecture

— One hundred twenty-seven 32 Kword/64-Kbyte

sectors

— Eight 4 Kword/8 Kbyte boot sectors

Compatibility with JEDEC standards

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent

write protection

Minimum 100,000 erase cycle guarantee per sector

20-year data retention at 125°C

PERFORMANCE CHARACTERISTICS

High performance

— 90 ns access time

— 25 ns page read times

— 0.5 s typical sector erase time

— 22 µs typical effective write buffer word programming

time: 16-word/32-byte write buffer reduces overall

programming time for multiple-word/byte updates

— 4-word/8-byte page read buffer

— 16-word/32-byte write buffer

Low power consumption (typical values at 3.0 V, 5

MHz)

— 30 mA typical active read current

— 50 mA typical erase/program current

— 1 µA typical standby mode current

Package options

— 48-pin TSOP

— 63-ball Fine-pitch BGA

— 64-ball Fortified BGA

SOFTWARE & HARDWARE FEATURES

Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

— Data# polling & toggle bits provide status

— Unlock Bypass Program command reduces overall

multiple-word programming time

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group

— Temporary Sector Unprotect: V

-level method of

changing code in locked sectors

— WP#/ACC input:

Write Protect input (WP#) protects top or bottom two

sectors regardless of sector protection settings

ACC (high voltage) accelerates programming time for

higher throughput during system production

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) indicates program or

erase cycle completion

Publication#

26190

Rev:

Amendment/8

Issue Date:

February 1, 2007

D A T A

S H E E T

GENERAL DESCRIPTION

The Am29LV640M is a 64 Mbit, 3.0 volt single power

supply flash memory device organized as 4,194,304

words o r 8,388 ,6 08 bytes. The device has an

8-bit/16-bit bus and can be programmed either in the

host system or in standard EPROM programmers.

An access time of 90, 100, 110, or 120 ns is available.

Note that each access time has a specific operating

voltage range (V

) and an I/O voltage range (V

), as

specified in

Product Selector Guide on page 6

and

Or-

dering Information on page 10.

The device is offered in

a 48-pin TSOP, 63-ball Fine-pitch BGA or 64-ball Forti-

fied BGA package. Each device has separate chip en-

able (CE#), write enable (WE#) and output enable

(OE#) controls.

Each device requires only a

single 3.0 volt power

supply

for both read and write functions. In addition to

a V

input, a high-voltage

accelerated program

(ACC)

function provides shorter programming times

through increased current on the WP#/ACC input. This

feature is intended to facilitate factory throughput dur-

ing system production, but can also be used in the

field if desired.

The device is entirely command set compatible with

the

JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The

sector erase architecture

allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle)

status bits

monitor the

Ready/Busy# (RY/BY#)

output to deter-

mine whether the operation is complete. To facilitate

programming, an

Unlock Bypass

mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

Hardware data protection

measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This is achieved in-system or via programming equip-

ment.

The

Erase Suspend/Erase Resume

feature allows

the host system to pause an erase operation in a given

sector to read or program any other sector and then

complete the erase operation. The

Program Sus-

pend/Program Resume

feature enables the host sys-

tem to pause a program operation in a given sector to

read any other sector and then complete the program

operation.

The

hardware RESET# pin

terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin can be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

The device reduces power consumption in the

standby mode

when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

The

Write Protect (WP#)

feature protects the top or

bottom two sectors by asserting a logic low on the

WP#/ACC pin. The protected sector is still protected

even during accelerated programming.

The

Secured Silicon Sector

provides a

128-word/256-byte area for code or data that can be

permanently protected. Once this sector is protected,

no further changes within the sector can occur.

AMD MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

Am29LV640MT/B

26190C8 February 1, 2007

D A T A

S H E E T

MIRRORBIT 64 MBIT DEVICE FAMILY

Device

LV065MU

LV640MT/B

LV640MH/L

LV641MH/L

LV640MU

Bus

x8/x16

x16

Sector Architecture

Uniform (64 Kbyte)

Boot (8 x 8 Kbyte

at top & bottom)

Uniform (64 Kbyte)

Uniform (32 Kword)

Packages

48-pin TSOP (std. & rev. pinout),

63-ball FBGA

48-pin TSOP, 63-ball Fine-pitch BGA,

64-ball Fortified BGA

56-pin TSOP (std. & rev. pinout),

64-ball Fortified BGA

48-pin TSOP (std. & rev. pinout)

64-ball Fortified BGA,

63-ball Fine-pitch BGA

Yes

RY/BY#

Yes

WP#, ACC

ACC only

WP#/ACC pin

Separate WP#

and ACC pins

ACC only

WP# Protection

No WP#

2 x 8 Kbyte

top or bottom

1 x 64 Kbyte

high or low

1 x 32 Kword

top or bottom

No WP#

RELATED DOCUMENTS

To download related documents, click on the following

links or go to

www.amd.com

→

Flash Memory

→

Prod-

uct Information

→

MirrorBit

→

Flash Information

→

Tech-

nical Documentation.

MirrorBit™ Flash Memory Write Buffer Programming

and Page Buffer Read

Implementing a Common Layout for AMD MirrorBit

and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs

AMD MirrorBit™ White Paper

February 1, 2007 26190C8

Am29LV640MT/B

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