LV96/LV98 Series 3.3 V
LVDS Clock Oscillators
January 2008
• Pletronics LV96/LV98 Series is a quartz crystal
controlled precision square wave generator
with an LVDS output.
• Solder pad compatible legacy LVDS oscillator
solutions.
• FR4 base using the LV93 or LV99 5x7 mm
ceramic packaged SMD device.
• Tape and Reel packaging is available.
• 10.9 to 670 MHZ
• Enable/Disable Function:
LV98
on pad 2
LV96
on pad 1
• Low Jitter
This series, LV96 and LV98, is not recommended for new designs.
Use LV93 or LV99 series for new designs
.
Pletronics Inc. certifies this device is in accordance with the
RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s
Weight of the Device: 0.40 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e4
Absolute Maximum Ratings:
Parameter
V
CC
Supply Voltage
Vi
Vo
Input Voltage
Output Voltage
Unit
-0.5V to +6.5V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
Thermal Characteristics
The maximum die or junction temperature is 155
o
C
The thermal resistance junction to board is 40 to 80
o
C/Watt depending on the solder pads, ground plane
and construction of the PCB.
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics standard warranty. Production
processsing does not necessarily include testing of all parameters.
Copyright © 2008, Pletronics Inc.
LV96/LV98 Series 3.3 V
LVDS Clock Oscillators
January 2008
Part Number:
LV9x
45
D
E
V
-125.0M
-XX
Packaging code or blank
T250 = 250 per Tape and Reel
T500 = 500 per Tape and Reel
T1K = 1000 per Tape and Reel
Frequency in MHZ
Supply Voltage V
CC
V
= 3.3V _ 10%
+
Temperature Range
blank
= -10 to +70
o
C
E
= -40 to +85
o
C
Series Model
Frequency Stability
45
= _ 50 ppm
+
44
= + 25 ppm
_
20
= + 20 ppm
_
Series Model
(x is 6 or 8)
Part Marking:
PLE LV9x
FF.FFF
M
C
YMDXX
Codes for Date Code YMD
Code
Year
Code
Month
Code
Day
Code
Day
Code
Day
1
1
D
13
T
25
7
2007
A
JAN
2
2
E
14
U
26
8
2008
B
FEB
3
3
F
15
V
27
9
2009
C
MAR
4
4
G
16
W
28
Marking Legend:
PLE = Pletronics
X = 6 or 8
FF.FFF
M = Frequency in MHZ
YMD
= Date of Manufacture (year-month-day)
All other marking is internal factory codes
0
2010
D
APR
E
MAY
5
5
H
17
X
29
1
2011
F
JUN
6
6
J
18
Y
30
G
JUL
7
7
K
19
Z
31
2
2012
H
AUG
8
8
L
20
J
SEP
9
9
M
21
K
OCT
A
10
N
22
L
NOV
B
11
P
23
M
DEC
C
12
R
24
www.pletronics.com
425-776-1880
2
LV96/LV98 Series 3.3 V
LVDS Clock Oscillators
January 2008
Electrical Specification for 3.30V _10% over the specified temperature range and the
+
frequency range of 10.9 MHz to 670 MHz
Item
Frequency Accuracy “45"
“44"
“20"
Output Waveform
Output High Level
Output Low Level
Differential Output (V
OD
)
Output Offset Voltage (V
OS
)
Differential Output Error (dV
OS
)
Output Symmetry
Output T
RISE
and T
FALL
Jitter
Min
-50
-25
-20
Max
+50
+25
+20
LVDS
Unit
ppm
Condition
For all supply voltages, load changes, aging for 1
year, shock, vibration and temperatures
--
0.90
250
1.125
--
47
150
-
-
1.60
--
450
1.375
50
53
230
0.6
2.8
-20
80
-
0.8
-
+20
+20
10
10
5
+70
+85
+125
Volts
Volts
mVolts
Volts
mVolts
%
pS
pS RMS
Referenced to 50% of amplitude or
crossing point
Vth is 20% and 80% of waveform
Measured from 12KHz to 20MHz from Fnominal
Measured from 10Hz to 20MHz from Fnominal
mA
mA
Kohm
Volts
Volts
uA
uA
nS
nS
mS
o
o
o
See load circuit
R1 = 50 ohms
Output Short Circuit Current
Vcc Supply Current
Enable/Disable
Internal Pull-up
V disable
V enable
Output leakage
V
OUT
= V
CC
V
OUT
= 0V
Enable
Disable time
Start up time
Operating Temperature Range
-
-
50
-
2.0
-20
-20
-
-
-
-10
-40
Vout = 0.0V
To Vcc (equivalent resistance)
Referenced to Ground
Referenced to Ground
Pad 1 low, device disabled
Time for output to reach a logic state
Time for output to reach a high Z state
Measured from the time Vcc = 3.0V
Standard Temperature Range
Extended Temperature Range
“E” Option
C
C
C
Storage Temperature Range
-55
Specifications with E/D open circuit or connected to V
CC
www.pletronics.com
425-776-1880
3
LV96/LV98 Series 3.3 V
LVDS Clock Oscillators
January 2008
Typical Phase-Noise Response
0
-20
-40
dBc/Hz
-60
-80
-100
-120
-140
-160
10
1,000
100,000
10,000,000
100MHz dBc/Hz
400MHz dBc/Hz
Frequency (Hz)
Load Circuit
Test Waveform
Symmetry
Vhigh
80%
50%
20%
Vlow
Trise
Tfall
Out
Out*
Showing Out Measurement only
www.pletronics.com
425-776-1880
4
LV96/LV98 Series 3.3 V
LVDS Clock Oscillators
January 2008
Reliability
: Environmental Compliance
Parameter
Mechanical Shock
Vibration
Solderability
Thermal Shock
Condition
MIL-STD-883 Method 2002, Condition B
MIL-STD-883 Method 2007, Condition A
MIL-STD-883 Method 2003
MIL-STD-883 Method 1011, Condition A
ESD Rating
Model
Human Body Model
Charged Device Model
Minimum Voltage
1500
1000
Conditions
MIL-STD-883 Method 3115
JESD 22-C101
Package Labeling
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Courier New
Bar code is 39-Full ASCII
(The part number will show as LV96xx or LV98xx)
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Arial
Layout and application information
For Optimum Jitter Performance, Pletronics recommends:
•
a ground plane under the device
•
no large transient signals (both current and voltage) should be routed under the device
•
do not layout near a large magnetic field such as a high frequency switching power supply
•
do not place near piezoelectric buzzers or mechanical fans.
As much ground plane and thermal paths that can be realized under and to the side of the part is desired
.
www.pletronics.com
425-776-1880
5
DSP 与 ARM 处理器
