Data Sheet
FEBRUARY 2000
LXT971
3.3V Dual-Speed Fast Ethernet Transceiver
General Description
The LXT971 is an IEEE compliant Fast Ethernet PHY
Transceiver that directly supports both 100BASE-TX and
10BASE-T applications. It provides a Media Independent
Interface (MII) for easy attachment to 10/100 Media
Access Controllers (MACs). The LXT971 also provides a
pseudo-ECL (PECL) interface for use with 100BASE-FX
fiber networks.
The LXT971 supports full-duplex operation at 10 Mbps
and 100 Mbps. Its operating condition can be set using
auto-negotiation, parallel detection, or manual control.
The LXT971 is fabricated with an advanced CMOS
process and requires only a single 3.3V power supply.
Revision 1.1
Features
• 3.3V Operation.
• Low power consumption (300 mW typical).
• Low-power “Sleep” mode.
• 10BASE-T and 100BASE-TX using a single RJ-45
connection.
• Supports auto-negotiation and parallel detection.
• MII interface with extended register capability.
• Robust baseline wander correction performance.
• 100BASE-FX fiber optic capable.
• Standard CSMA/CD or full-duplex operation.
• Configurable via MDIO serial port or hardware
control pins.
• Integrated, programmable LED drivers.
• 64-pin Plastic Ball Grid Array (PBGA).
• LXT971BC - Commercial (0
°
to 70
°
C ambient).
• LXT971BE - Extended (-40
°
to 85
°
C ambient).
• 64-pin Low-profile Quad Flat Package (LQFP).
• LXT971LC - Commercial (0
°
to 70
°
C ambient).
• LXT971LE - Extended (-40
°
to 85
°
C ambient).
Applications
• Combination 10BASE-T/100BASE-TX or
100BASE-FX Network Interface Cards (NICs)
• 10/100 PCMCIA Cards
• Cable Modems and Set-Top Boxes
LXT971 Block Diagram
RESET
ADDR<4:0>
MDIO
MDC
MDINT
MDDIS
TX_EN
TX PCS
T X D <3:0>
TX_ER
TX_CLK
Parallel/Serial
Converter
Management /
Mode Select
Logic
Pwr Supply
Register Set
Clock
Generator
VCC
GND
PWRDWN
REFCLK
TxSLEW<1:0>
Manchester
Encoder
Scrambler
& Encoder
Auto
Negotiation
Register
Set
10
100
OSP
™
Pulse
Shaper
TP
Driver
+
-
+
-
JTAG
5
TDIO,
TMS,
TCK,
TRST
TPFOP
TP / Fiber
Out
TPFON
ECL
Driver
L E D / C F G <3:1>
Collision
Detect
OSP
™
COL
Clock
Generator
Media
Select
Adaptive EQ with
Baseline Wander
Cancellation
+
100TX
RX_CLK
R X D <3:0>
RXDV
CRS
RX_ER
RX PCS
Carrier Sense
Data Valid
Error Detect
Serial-to-
Parallel
Converter
10
Manchester
Decoder
-
+
100FX
OSP
™
Slicer
TP / Fiber
In
TPFIP
TPFIN
SD/TP
Decoder &
100
Descrambler
-
+
10BT
-
Refer to www.level1.com for most current information.
)
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
TABLE OF CONTENTS
Pin Assignments
................................................... 4
Signal Descriptions
............................................... 7
Functional Description
........................................ 11
Introduction
....................................................... 11
OSP™ Architecture
.......................................... 11
Comprehensive Functionality............................
12
Network Media/Protocol Support.....................
12
10/100 Network Interface..................................
12
Twisted-Pair Interface
.................................. 12
Fiber Interface..............................................
12
Fault Detection and Reporting
..................... 12
Remote Fault
.......................................... 12
Far-End Fault..........................................
12
MII Data Interface
............................................. 13
Configuration Management Interface................
13
MDIO Management Interface
...................... 13
MDIO Addressing
................................... 13
MDIO Frame Structure
........................... 13
MII Interrupts
.......................................... 14
Hardware Control Interface..........................
14
Operating Requirements...................................
15
Power Requirements
........................................ 15
Clock Requirements..........................................
15
External Crystal Oscillator
........................... 15
Initialization........................................................
15
MDIO Control Mode
.......................................... 15
Hardware Control Mode....................................
15
Reduced Power Modes
.................................... 16
Hardware Power Down................................
16
Software Power Down
................................. 16
Sleep Mode..................................................
16
Reset
................................................................ 16
Hardware Configuration Settings
...................... 17
Establishing Link...............................................
18
Auto-Negotiation
............................................... 18
Base Page Exchange
.................................. 18
Next Page Exchange
................................... 18
Controlling Auto-Negotiation........................
18
Parallel Detection..............................................
18
MII Operation......................................................19
MII Clocks
.........................................................19
Transmit Enable
................................................19
Receive Data Valid
............................................19
Carrier Sense
....................................................19
Error Signals
.....................................................19
Collision.............................................................19
Loopback...........................................................21
Operational Loopback..................................21
Test Loopback..............................................21
100 Mbps Operation
..........................................22
100BASE-X Network Operation
........................22
Collision Indication
............................................25
100BASE-X Protocol Sublayer Operations
.......26
PCS Sublayer
..............................................26
Preamble Handling
.................................26
Dribble Bits
.............................................26
4B/5B Coding Table
.....................................27
PMA Sublayer
..............................................28
Link
.........................................................28
Link Failure Override
..............................28
Carrier Sense..........................................28
Receive Data Valid
.................................28
Twisted-Pair PMD Sublayer
.........................29
Scrambler/Descrambler
..........................29
Baseline Wander Correction
...................29
Polarity Correction
..................................29
Programmable Slew Rate Control
..........29
Fiber PMD Sublayer.....................................29
10 Mbps Operation
............................................30
10T Preamble Handling
....................................30
10T Carrier Sense.............................................30
10T Dribble Bits.................................................30
10T Link Integrity Test
.......................................30
Link Failure
..................................................30
10T SQE (Heartbeat)
........................................30
10T Jabber
........................................................30
10T Polarity Correction
.....................................30
2
LXT971 Table of Contents
Monitoring Operations
......................................31
Monitoring Auto-Negotiation..............................31
Monitoring Next Page Exchange..................31
LED Functions...................................................31
LED Pulse Stretching
...................................32
Boundary Scan (JTAG) Functions....................33
Boundary Scan Interface
...................................33
State Machine
...................................................33
Instruction Register
...........................................33
Boundary Scan Register (BSR).........................33
Application Information
.......................................34
Magnetics Information
.......................................34
Typical Twisted-Pair Interface
...........................36
Typical MII Interface
..........................................37
Typical Fiber Interface
.......................................38
Preliminary Test Specifications
..........................39
Electrical Parameters
........................................39
Absolute Maximum Ratings...............................39
Operating Conditions.........................................39
Digital I/O Characteristics
..................................40
Digital I/O Characteristics - MII Pins..................40
I/O Characteristics - REFCLK/XI and XO Pins
..40
I/O Characteristics - LED/CFG Pins
..................41
100BASE-TX Transceiver Characteristics.........41
100BASE-FX Transceiver Characteristics.........41
10BASE-T Transceiver Characteristics
.............42
10BASE-T Link Integrity Timing Characteristics42
Timing Diagrams
................................................43
100BASE-TX Receive Timing - 4B Mode
.........43
100BASE-TX Transmit Timing - 4B Mode
........44
100BASE-FX Receive Timing
...........................45
100BASE-FX Transmit Timing
..........................46
10BASE-T Receive Timing................................47
10BASE-T Transmit Timing
...............................48
10BASE-T Jab and Unjab Timing......................49
Auto Negotiation and Fast Link Pulse Timing....50
MDIO Timing
.....................................................51
Power-Up Timing...............................................52
RESET Pulse Width and Recovery Timing
.......52
Register Definitions..............................................53
Control Register (Address 0)
.............................56
Status Register (Address 1)
..............................57
PHY Identification Register 1 (Address 2)
........ 58
PHY Identification Register 2 (Address 3)
........ 58
A/N Advertisement Register (Address 4)..........
59
A/N Link Partner Ability Register (Address 5)...
60
A/N Expansion Register (Address 6)
................ 61
A/N Next Page Transmit Register (Address 7)
. 62
A/N Link Partner Next Page Receive Register
(Address 8)
....................................................... 62
Port Configuration Register (Address 16).........
63
Quick Status Register (Address 17)
................. 64
Interrupt Enable Register (Address 18)
............ 65
Interrupt Status Register (Address 19)
............. 66
LED Configuration Register (Address 20)
........ 67
Transmit Control Register (Address 30)
........... 69
Package Specifications
....................................... 70
Revision History...................................................
72
3
LXT971 3.3V Dual-Speed Fast Ethernet Transceiver
PIN ASSIGNMENTS
Figure 1: 64-Pin PBGA Pin Assignments
1
MDINT
2
CRS
3
TXD3
4
TXD0
5
RX_ER
6
VCCD
7
RX_DV
8
RXD0
A
REFCLK/XI COL
TXD2
TX_EN TX_ER RX_CLK
N/C
RXD1
B
XO
RESET
GND
TXD1
TX_CLK
GND
N/C
RXD2
C
TxSLEW0 TxSLEW1 MDDIS
GND
VCCIO
RXD3
N/C
MDIO
D
ADDR0
ADDR1
GND
GND
VCCIO
LED/CFG1 M D C P W R D W N
E
ADDR3
ADDR2
GND
GND
TDI
TMS LED/CFG2 LED/CFG3
F
ADDR4
SD/TP
VCCA
VCCA
TDO
TCK
TEST1
TEST0
G
RBIAS
TPFOP
TPFON
TPFIP
TPFIN
TRST
SLEEP
PAUSE
H
Bottom Mark
LXT971
)
4
LXT971 Pin Assignments
PIN ASSIGNMENTS
Figure 2: 64-Pin LQFP Pin Assignments
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
MDINT
CRS
COL
GND
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
TX_ER
RX_ER
RX_CLK
VCCD
GND
RX_DV
REFCLK/XI
XO
MDDIS
RESET
TXSLEW0
TXSLEW1
GND
VCCIO
N/C
N/C
GND
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LXT971
)
RXD0
RXD1
RXD2
RXD3
N/C
MDC
MDIO
GND
VCCIO
PWRDWN
LED/CFG1
LED/CFG2
LED/CFG3
TEST1
TEST0
PAUSE
RBIAS
GND
TPFOP
TPFON
VCCA
VCCA
TPFIP
TPFIN
GND
SD/TP
TDI
TDO
TMS
TCK
TRST
SLEEP
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
5
