Integrated
Circuit
Systems, Inc.
Preliminary Information
M1020/21
VCSO B
ASED
C
LOCK
PLL
G
ENERAL
D
ESCRIPTION
The M1020/21 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1020/21 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
MR_SEL3
GND
NC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
28
29
30
31
32
33
34
35
36
M1020
M1021
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL0
P_SEL1
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
F
EATURES
◆
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
◆
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Lock (LOL) output pin
◆
Narrow Bandwidth control input (NBW pin)
◆
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) / SDH
(G.813) MTIE and TDEV compliance during reselection
◆
Pin-selectable feedback and reference divider ratios
◆
Industrial temperature grade available
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M1020-11-155.5200 or M1021-11-155.5200
Input Reference
Clock (MHz)
(M1020)
(M1021)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
PLL Ratio
(Pin Selectable)
(M1020)
(M1021)
Output Clock
(MHz)
(Pin Selectable)
19.44 or 38.88
77.76
155.52
622.08
8 or 4
2
1
0.25
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
M1020/21
NBW
LOL
MUX
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
MR_SEL3:0
4
Phase
Detector
0
1
R Div
VCSO
M Divider
M/R Divider
LUT
P Divider
(1, 2, or TriState)
TriState
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL1:0
2
P Divider
LUT
Figure 2: Simplified Block Diagram
M1020/21 Datasheet Rev 0.1
M1020/21 VCSO Based Clock PLL
Revised 11Nov2003
●
Integrated Circuit Systems, Inc.
Communications Modules
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M1020/21
VCSO B
ASED
C
LOCK
PLL
Preliminary Information
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
13
15
16
17
18
20
21
22
23
24
25
27
28
29
30
31
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
FOUT1
nFOUT1
FOUT0
nFOUT0
P_SEL1
P_SEL0
nDIF_REF1
DIF_REF1
REF_SEL
nDIF_REF0
DIF_REF0
NC
MR_SEL3
MR_SEL2
MR_SEL0
MR_SEL1
LOL
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Output
Output
No internal terminator
No internal terminator
Power supply ground connections.
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 6.
Power supply connection, connect to +
3.3
V.
Clock output 1. Differential LVPECL (CML, LVDS available).
Clock output 0. Differential LVPECL (CML, LVDS available).
, P divider selection. LVCMOS/LVTTL. See Table 5,
Internal pull-down resistor
1
Post-PLL Look-Up Table (LUT), on pg. 4.
P Divider
Input
Input
Input
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
Reference clock input selection. LVCMOS/LVTTL:
Internal pull-down resistor
1
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
No internal connection.
Internal pull-down resistor
1
M and R divider value selection. LVCMOS/ LVTTL.
See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
on pg. 3.
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase.
3
Logic
1
indicates loss of lock.
Logic
0
indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100kΩ
.
Logic
0
- Wide bandwidth
, R
IN
= 100kΩ
.
Internal nodes. Connection to these pins can cause erratic
device operation.
Table 2: Pin Descriptions
Biased to Vcc/2
2
Biased to Vcc/2
2
Input
Output
32
34, 35, 36
NBW
DNC
Input
Internal pull-UP resistor
1
Do Not Connect.
Note 1: For typical values of internal pull-down and pull-UP resistors, see
DC Characteristics
on pg. 8.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See
Differential Inputs Biased to VCC/2
on pg. 8.
Note 3: See
LVCMOS Output
in
DC Characteristics
on pg. 8.
M1020/21 Datasheet Rev 0.1
Integrated Circuit Systems, Inc.
●
2 of 10
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Revised 11Nov2003
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M1020/21
VCSO B
ASED
C
LOCK
PLL
Preliminary Information
D
ETAILED
B
LOCK
D
IAGRAM
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
C
LOOP
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M1020/21
NBW
LOL
MUX
OP_IN
nOP_IN
OP_OUT
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
Phase
Detector
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
MR_SEL3:0
4
0
R Div
R
IN
Loop Filter
Amplifier
1
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
M Divider
M/R Divider
LUT
P Divider
(FOUT0: 1, 2, or TriState),
(FOUT1: 1, 2, or TriState)
TriState
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL1:0
2
P Divider
LUT
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
M and R Divider Look-Up Tables (LUT)
The
MR_SEL3:0
pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1020 and M1021 are defined in
Tables 3 and 4 respectively.
M1020 M/R Divider LUT
Phase Det.
Total
Fin for
Freq. for
MR_SEL3:0
M Div R Div PLL
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
Tables 3 and 4
provide example Fin and phase
detector frequencies with
155.52MHz
VCSO
devices (M1020-11-155.5200 and
M1021-11-155.5200).
See “Ordering Information” on pg. 10.
M1021 M/R Divider LUT
Phase Det.
Total
Fin for
Freq. for
MR_SEL3:0
M Div R Div PLL
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
8
32
128
512
2
8
32
128
1
4
16
64
1
4
16
1
4
16
64
1
4
16
64
1
4
16
64
4
16
64
8
8
8
8
2
2
2
2
1
1
1
1
N/A
0.25
0.25
0.25
19.44
19.44
19.44
19.44
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
622.08
622.08
622.08
19.44
4.86
1.215
0.30375
77.76
19.44
4.86
1.215
155.52
38.88
9.72
2.43
N/A
155.52
38.88
9.72
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
16
64
256
2
8
32
128
1
4
16
64
1
4
16
1
4
16
64
1
4
16
64
1
4
16
64
4
16
64
4
4
4
4
2
2
2
2
1
1
1
1
N/A
0.25
0.25
0.25
38.88
38.88
38.88
38.88
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
622.08
622.08
622.08
38.88
9.72
2.43
0.6075
77.76
19.44
4.86
1.215
155.52
38.88
9.72
2.43
N/A
155.52
38.88
9.72
Test Mode
1
Test Mode
1
Table 3: M1020 M/R Divider LUT
Table 4: M1021 M/R Divider LUT
Note 1: Factory test mode; do not use.
Note 1: Factory test mode; do not use.
M1020/21 Datasheet Rev 0.1
Integrated Circuit Systems, Inc.
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Communications Modules
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Revised 11Nov2003
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Systems, Inc.
General Guidelines for M and R Divider Selection
M1020/21
VCSO B
ASED
C
LOCK
PLL
Preliminary Information
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
General guidelines for M/R divider selection (see
following pages for more detail):
•
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44MHz
. The
LOL
pin should
not be used during loop timing mode.
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be
5MHz
or
greater. Low phase detector frequencies make
LOL
overly sensitive, and higher phase detector
frequencies make
LOL
less sensitive.
•
P Divider Look-Up Table (LUT)
The
P_SEL1
and
P_SEL0
pins select the post-PLL divider
values P1 and P0. The output frequency of the SAW
can be divided by
1
or
2,
or the outputs can be TriStated.
The outputs can be placed into the valid state
combinations as listed in Table 5.
P Values
P_SEL1:0
for FOUT0 for FOUT1
M1020-155.5200 or M1021-155.5200
Implementation of single-ended input has been
facilitated by biasing
nDIF_REF0
and
nDEF_REF1
to Vcc/2,
with 50kΩ to Vcc and 50kΩ to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
Output Frequency (MHz)
FOUT0
FOUT1
LVCMOS/
LVTTL
50k
Ω
X
VCC
50k
Ω
MUX
0
0
0
1
1
0
1
0
1
2
2
1
1
2
1
TriState TriState
77.76 77.76
155.52 155.52
77.76 155.52
N/A
N/A
VCC
127
Ω
50k
Ω
1
Table 5: P Divider Look-Up Table (LUT)
LVPECL
82
Ω
VCC
127
Ω
50k
Ω
VCC
50k
Ω
F
UNCTIONAL
D
ESCRIPTION
The M1020/21 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in
Tables 3 and 4 on pg. 3.
These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
The M1020/21 includes a Loss of Lock (
LOL
) indicator,
which provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide
SONET/SDH MTIE and TDEV compliance during a
reference clock reselection.
M1020/21 Datasheet Rev 0.1
Integrated Circuit Systems, Inc.
●
82
Ω
50k
Ω
REF_SEL
M1020/21
Figure 4: Input Reference Clocks
Differential LVPECL Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in
Figure 4
(the 127Ω
and 82Ω resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50Ω load termination and the V
TT
bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(
DIF_REF0
or
DIF_REF1
). The inverting reference input pin
(
nDIF_REF0
or
nDIF_REF1
) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or
nDEF_REF1)
is left floating (not
connected), the input will self-bias at VCC/2.
4 of 10
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PLL Operation
The M1020/21 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector.
The output of the “R” divider is fed into the minus input
of the phase detector. The phase detector compares its
two inputs. The phase detector output, filtered
externally, causes the VCSO to increase or decrease in
speed as needed to phase- and frequency-lock the
VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
M1020/21
VCSO B
ASED
C
LOCK
PLL
Preliminary Information
Loss of Lock Indicator (LOL) Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives
LOL
to logic
0
. Under
circumstances when the VCSO cannot lock to the input
(as measured by a greater than 4 ns discrepancy
between the feedback and reference clock rising edges
at the LOL Phase Detector) the
LOL
output goes to logic
1. The
LOL
pin will return back to logic
0
when the phase
detector error is less than 2 ns. The loss of lock
indicator is a low current LVCMOS output.
Guidelines for Using LOL
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
-
Fvcso
=
Fin
×
---
R
For the available M divider and R divider look-up table
combinations,
Tables 3 and 4 on pg. 3
list the Total PLL
Ratio as well as Fin when using the
M1020-11-155.5200
or
the
M1021-11-155.5200
.
(See “Ordering Information” on pg.
10.)
Post-PLL Divider
The M1020/21 also features a post-PLL (P) divider.
By using the P Divider, the device’s output frequency
(Fout) can be the VCSO center frequency (Fvcso) or
1/2 Fvcso, or 0.
The
P_SEL0
and
P_SEL1
pins select the value for the P
divider. (See Table 5 on pg. 4.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
M
Fvcso
-
Fout
=
-------------------
=
Fin
×
-----------------
P
R
×
P
M
In a given application, the magnitude of peak-to-peak
jitter at the phase detector will usually increase as the R
divider is increased. If the
LOL
pin will be used to detect
an unusual clock condition, or a clock fault, the
MR_SEL3:0
pins should be set to provide a phase detector
frequency of
5MHz
or greater. Otherwise, false
LOL
indications may result. A phase detector frequency of
10MHz
or greater is desirable when reference jitter is
over
500ps
, or when the device is used within a noisy
system environment. Refer to
Tables 3 and 4 on pg. 3
for phase detector frequency when using the
M1020-11-155.5200
or the
M1021-11-155.5200
.
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the
FOUT
and
nFOUT
pins of the device. A
logic
0
is then present on the clock net. The impedance
of the clock net is then set to 50Ω by the external circuit
resistors. (This is in distinction to a CMOS output in
TriState, in which case the net goes to a high
impedance and the logic value floats.) The 50Ω
impedance level of the LVPECL TriState allows
manufacturing In-circuit Test to drive the clock net with
an external 50Ω generator to validate the integrity of
clock net and the clock load.
Any unused output (single-ended or differential)
should be left unconnected (floating) in system
application. This minimizes output switching current
and therefore minimizes noise modulation of VCSO.
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
M1020/21 Datasheet Rev 0.1
Integrated Circuit Systems, Inc.
●
5 of 10
Communications Modules
●
Revised 11Nov2003
w w w. i c s t . c o m
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