M24512-W M24512-R M24512-DF
Datasheet
512-Kbit serial I²C bus EEPROM
Features
•
SO8N (MN)
TSSOP8 (DW)
169 mil width
150 mil width
•
•
UFDFPN8 (MC)
DFN8 - 2x3 mm
•
•
WLSCP (CS)
WLSCP (CU)
Unsawn wafer
Product status link
M24512-W
M24512-R
M24512-DF
•
•
•
•
•
•
Compatible with following I
2
C bus modes:
–
1 MHz
–
400 kHz
–
100 kHz
Memory array:
–
512 Kbit (64 Kbyte) of EEPROM
–
Page size: 128 byte
–
Additional write lockable page (M24512-D order codes)
Single supply voltage and high speed:
–
1 MHz clock from 1.7 V to 5.5 V
Write time:
–
Byte write within 5 ms
–
Page write within 5 ms
Operating temperature range:
–
-40 °C up to +85 °C
Random and sequential read modes
Write protect of the whole memory array
Enhanced ESD/latch-Up protection
More than 4 million write cycles
More than 200-years data retention
Packages:
–
–
–
–
–
SO8 ECOPACK2
®
TSSOP8 ECOPACK2
®
UFDFPN8 ECOPACK2
®
WLCSP ECOPACK2
®
Unsawn wafer (each die is tested)
DS6520
-
Rev 31
-
October 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
M24512-W M24512-R M24512-DF
Description
1
Description
The M24512 is a 512-Kbit I
2
C-compatible EEPROM (electrically erasable programmable memory) organized as
64 K × 8 bits.
The
M24512-W
can operate with a supply voltage from 2.5 V to 5.5 V, the
M24512-R
can operate with a supply
voltage from 1.8 V to 5.5 V, and the
M24512-DF
can operate with a supply voltage from 1.7 V to 5.5 V. All these
devices operate with a clock frequency of 1 MHz (or less), over an ambient temperature range of –40 °C / +85 °C.
The M24512-D offers an additional page, named the identification page (128 byte). The identification page can be
used to store sensitive application parameters which can be (later) permanently locked in read-only mode.
Figure 1.
Logic diagram
VCC
3
E0-E2
M24xxx
SCL
WC
SDA
VSS
Table 1.
Signal names
Signal name
E2, E1, E0
SDA
SCL
WC
V
CC
V
SS
Chip enable
Serial data
Serial clock
Write control
Supply voltage
Ground
Function
Input
I/O
Input
Input
-
-
Direction
Figure 2.
8-pin package connections, top view
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
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M24512-W M24512-R M24512-DF
Description
Figure 3.
WLCSP connections
1
A
B
C
D
E
V
SS
E2
SDA
2
3
V
CC
3
V
CC
2
1
SDA
A
B
SCL
WC
E1
E0
E0
WC
SCL
E2
E1
V
SS
C
D
E
Marking side
(top view)
Bump side
(bottom view)
Table 2.
Signal vs. bump position
Position
1
2
3
A
SDA
-
V
CC
B
-
SCL
-
C
E2
-
WC
D
-
E1
-
E
V
SS
-
E0
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M24512-W M24512-R M24512-DF
Signal description
2
2.1
Signal description
Serial clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on
SDA(out).
2.2
Serial data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that
may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be
connected from serial data (SDA) to V
CC
(Figure
12
indicates how to calculate the value of the pull-up resistor).
2.3
Chip enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2,
b1) of the 7-bit device select code (see
Table 3).
These inputs must be tied to V
CC
or V
SS
, as shown in
Figure 4.
When not connected (left floating), these inputs are read as low (0).
Figure 4.
Chip enable inputs connection
VCC
VCC
M24xxx
Ei
M24xxx
Ei
VSS
VSS
2.4
Write control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write
operations are disabled to the entire memory array when write control (WC) is driven high. Write operations are
enabled when write control (WC) is either driven low or left floating.
When write control (WC) is driven high, device select and address bytes are acknowledged, data bytes are not
acknowledged.
2.5
V
SS
(ground)
V
SS
is the reference for the V
CC
supply voltage.
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M24512-W M24512-R M24512-DF
Supply voltage (VCC)
2.6
2.6.1
Supply voltage (V
CC
)
Operating supply voltage (V
CC
)
Prior to selecting the memory and issuing instructions to it, a valid and stable V
CC
voltage within the specified
[V
CC
(min), V
CC
(max)] range must be applied (see Operating conditions in
Section 8 DC and AC parameters).
In
order to secure a stable DC supply voltage, it is recommended to decouple the V
CC
line with a suitable capacitor
(usually of the order of 10 nF to 100 nF) close to the V
CC
/V
SS
package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write
instruction, until the completion of the internal write cycle (t
W
).
2.6.2
Power-up conditions
The V
CC
voltage has to rise continuously from 0 V up to the minimum V
CC
operating voltage (see Operating
conditions in
Section 8 DC and AC parameters).
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.
At power-up, the device does not respond to any instruction until V
CC
has reached the internal reset threshold
voltage. This threshold is lower than the minimum V
CC
operating voltage (see Operating conditions in
Section 8 DC and AC parameters).
When V
CC
passes over the POR threshold, the device is reset and enters
the standby power mode; however, the device must not be accessed until V
CC
reaches a valid and stable DC
voltage within the specified [V
CC
(min), V
CC
(max)] range (see Operating conditions in
Section 8 DC and AC
parameters).
In a similar way, during power-down (continuous decrease in V
CC
), the device must not be accessed when V
CC
drops below V
CC
(min). When V
CC
drops below the power-on-reset threshold voltage, the device stops responding
to any instruction sent to it.
2.6.4
Power-down conditions
During power-down (continuous decrease in V
CC
), the device must be in the standby power mode (mode reached
after decoding a stop condition, assuming that there is no internal write cycle in progress).
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NXP MCU
