M27C160
16 Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM
s
5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
ACCESS TIME: 50ns
BYTE-WIDE or WORD-WIDE
CONFIGURABLE
16 Mbit MASK ROM REPLACEMENT
LOW POWER CONSUMPTION
– Active Current 70mA at 8MHz
– Standby Current 100µA
42
42
s
s
s
s
1
1
FDIP42W (F)
PDIP42 (B)
s
s
s
PROGRAMMING VOLTAGE: 12.5V ± 0.25V
PROGRAMMING TIME: 50µs/word
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: B1h
SDIP42 (S)
42
1
DESCRIPTION
The M27C160 is a 16 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large data or program
storage and is organised as either 2 Mbit words of
8 bit or 1 Mbit words of 16 bit. The pin-out is com-
patible with a 16 Mbit Mask ROM.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written rapidly to
the device by following the programming proce-
dure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C160 is offered in PDIP42, SDIP42, PLCC44
and SO44 packages.
44
1
PLCC44 (K)
SO44 (M)
Figure 1. Logic Diagram
VCC
20
A0-A19
15
Q15A–1
Q0-Q14
E
G
BYTEVPP
M27C160
VSS
AI00739B
January 2002
1/19
M27C160
Figure 2. DIP Connections
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
42
2
41
3
40
4
39
5
38
6
37
7
36
35
8
9
34
10
33
M27C160
32
11
31
12
30
13
29
14
28
15
27
16
26
17
25
18
24
19
20
23
22
21
AI00740
Figure 3. PLCC Connections
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTEVPP
VSS
Q15A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
A4
A3
A2
A1
A0
E
VSS
G
Q0
Q8
Q1
A5
A6
A7
A17
A18
VSS
A19
A8
A9
A10
A11
1 44
A12
A13
A14
A15
A16
BYTEVPP
VSS
Q15A–1
Q7
Q14
Q6
12
M27C160
34
23
Q9
Q2
Q10
Q3
Q11
NC
VCC
Q4
Q12
Q5
Q13
AI03012
Figure 4. SO Connections
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
44
1
43
2
3
42
4
41
40
5
39
6
38
7
37
8
36
9
35
10
34
11
M27C160
33
12
32
13
31
14
30
15
29
16
17
28
18
27
19
26
20
25
21
24
22
23
AI01264
Table 1. Signal Names
NC
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTEVPP
VSS
Q15A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
A0-A19
Q0-Q7
Q8-Q14
Q15A–1
E
G
BYTEV
PP
V
CC
V
SS
NC
Address Inputs
Data Outputs
Data Outputs
Data Output / Address Input
Chip Enable
Output Enable
Byte Mode / Program Supply
Supply Voltage
Ground
Not Connected Internally
2/19
M27C160
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
Read Word-wide
Read Byte-wide Upper
Read Byte-wide Lower
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = V
IH
or V
IL
, V
ID
= 12V ± 0.5V.
E
V
IL
V
IL
V
IL
V
IL
V
IL
Pulse
V
IH
V
IH
V
IH
V
IL
G
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IH
X
V
IL
BYTEV
PP
V
IH
V
IL
V
IL
X
V
PP
V
PP
V
PP
X
V
IH
A9
X
X
X
X
X
X
X
X
V
ID
Q15A–1
Data Out
V
IH
V
IL
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Code
Q8-Q14
Data Out
Hi-Z
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Q7-Q0
Data Out
Data Out
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q7
0
1
Q6
0
0
Q5
1
1
Q4
0
1
Q3
0
0
Q2
0
0
Q1
0
0
Q0
0
1
Hex Data
20h
B1h
Note: Outputs Q15-Q8 are set to '0'.
3/19
M27C160
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
Standard
≤
20ns
0.4V to 2.4V
0.8V and 2V
Figure 5. AC Testing Input Output Waveform
Figure 6. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01822
1N914
3.3kΩ
Standard
2.4V
OUT
CL
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance
(1)
(T
A
= 25 °C, f = 1 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance (except BYTEV
PP
)
Input Capacitance (BYTEV
PP
)
Output Capacitance
Test Condition
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
Min
Max
10
120
12
Unit
pF
pF
pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
The operating modes of the M27C160 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V
PP
and 12V on A9 for the
Electronic Signature.
Read Mode
The M27C160 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV
PP
pin. When BYTEV
PP
is at V
IH
the Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEV
PP
pin is at V
IL
the Byte-wide or-
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at V
IL
the
lower 8 bits of the 16 bit data are selected and with
A–1 at V
IH
the upper 8 bits of the 16 bit data are
selected.
The M27C160 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
AVQV
) is equal to the delay
from E to output (t
ELQV
). Data is available at the
output after a delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
4/19
M27C160
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70 °C or –40 to 85 °C; V
CC
= 5V ± 5% or 5V ± 10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 8MHz
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
I
CC1
I
CC2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
I
OL
= 2.1mA
I
OH
= –400µA
2.4
E = V
IH
E > V
CC
– 0.2V
V
PP
= V
CC
–0.3
2
50
1
100
10
0.8
V
CC
+ 1
0.4
mA
mA
µA
µA
V
V
V
V
Min
Max
±1
±10
70
Unit
µA
µA
mA
I
CC
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Standby Mode
The M27C160 has a standby mode which reduces
the active current from 50mA to 100µA. The
M27C160 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I
CC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E.
The magnitude of the transient current peaks is
dependent on the capacitive and inductive loading
of the device outputs. The associated transient
voltage peaks can be suppressed by complying
with the two line output control and by properly se-
lected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor is used on every
device between V
CC
and V
SS
. This should be a
high frequency type of low inherent inductance
and should be placed as close as possible to the
device. In addition, a 4.7µF electrolytic capacitor
should be used between V
CC
and V
SS
for every
eight devices.
This capacitor should be mounted near the power
supply connection point. The purpose of this ca-
pacitor is to overcome the voltage drop caused by
the inductive effects of PCB traces.
5/19
