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M27V402

4 Mbit (256Kb x16) Low Voltage UV EPROM and OTP EPROM

NOT FOR NEW DESIGN

M27V402 is replaced by the M27W402

LOW VOLTAGE READ OPERATION:

3V to 3.6V

ACCESS TIME: 120ns

LOW POWER CONSUMPTION:

– Active Current 15mA at 5MHz

– Standby Current 20µA

PROGRAMMING VOLTAGE: 12.75V ± 0.25V

PROGRAMMING TIME: 100µs/word

ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: 8Dh

FDIP40W (F)

DESCRIPTION

The M27V402 is a low voltage, low power 4 Mbit

UV erasable and electrically programmable

EPROM, ideally suited for handheld and portable

microprocessor systems requiring large programs.

It is organized as 262,144 by 16 bits.

The M27V402 operates in the read mode with a

supply voltage as low as 3V. The decrease in op-

erating power allows either a reduction of the size

of the battery or an increase in the time between

battery recharges.

The FDIP40W (window ceramic frit-seal package)

has a transparent lid which allows the user to ex-

pose the chip to ultraviolet light to erase the bit pat-

tern. A new pattern can then be written to the

device by following the programming procedure.

For applications where the content is programmed

only one time and erasure is not required, the

M27V256 is offered in PDIP40, PLCC44 and

TSOP40 (10 x 20 mm) packages.

-O

Figure 1. Logic Diagram

PLCC44 (K)

VCC

PDIP40 (B)

TSOP40 (N)

10 x 20 mm

VPP

A0-A17

Q0-Q15

M27V402

VSS

AI01819

July 2000

This is information on a product still in production but not recommended for new designs.

1/15

M27V402

Figure 2A. DIP Connections

VPP

Q15

Q14

Q13

Q12

Q11

Q10

VSS

M27V402

AI01862

Figure 2B. LCC Connections

VCC

A17

A16

A15

A14

A13

A12

A11

A10

VSS

Q12

Q11

Q10

VSS

Q13

Q14

Q15

VPP

VCC

A17

A16

A15

A14

1 44

A13

A12

A11

A10

VSS

M27V402

Figure 2C. TSOP Connections

A10

A11

A12

A13

A14

A15

A16

A17

VCC

VPP

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

VSS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VSS

-O

Table 1. Signal Names

A0-A17

Q0-Q15

Address Inputs

Data Outputs

Chip Enable

Output Enable

Program Supply

Supply Voltage

Ground

Not Connected Internally

AI01820

M27V402

(Normal)

AI01821

2/15

M27V402

Table 2. Absolute Maximum Ratings

(1)

Symbol

BIAS

STG

IO (2)

A9 (2)

Parameter

Ambient Operating Temperature

(3)

Temperature Under Bias

Storage Temperature

Input or Output Voltage (except A9)

Supply Voltage

A9 Voltage

Program Supply Voltage

Value

–40 to 125

–50 to 125

–65 to 150

–2 to 7

–2 to 13.5

–2 to 14

Unit

°C

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC

voltage on Output is V

+0.5V with possible overshoot to V

+2V for a period less than 20ns.

3. Depends on range.

Table 3. Operating Modes

Mode

Read

Output Disable

Program

Verify

Program Inhibit

Standby

Electronic Signature

Note: X = V

or V

, V

= 12V ± 0.5V.

Pulse

Table 4. Electronic Signature

Identifier

Manufacturer’s Code

Device Code

Note: Outputs Q15-Q8 are set to '0'.

-O

or V

Q15-Q0

Data Out

Hi-Z

Data In

Data Out

Hi-Z

Codes

Hex Data

20h

8Dh

3/15

M27V402

Table 5. AC Measurement Conditions

High Speed

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

≤

10ns

0 to 3V

1.5V

Standard

≤

20ns

0.4V to 2.4V

0.8V and 2V

Figure 3. AC Testing Input Output Waveform

Figure 4. AC Testing Load Circuit

1.3V

High Speed

1.5V

DEVICE

UNDER

TEST

2.0V

0.8V

AI01822

1N914

3.3kΩ

Standard

2.4V

0.4V

CL = 30pF for High Speed

CL = 100pF for Standard

CL includes JIG capacitance

Table 6. Capacitance

(1)

= 25 °C, f = 1 MHz)

Symbol

OUT

Parameter

Input Capacitance

Output Capacitance

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION

The operating modes of the M27V402 are listed in

the Operating Modes table. A single power supply

is required in the read mode. All inputs are TTL

levels except for V

and 12V on A9 for Electronic

Signature.

Read Mode

The M27V402 has two control functions, both of

which must be logically active in order to obtain

data at the outputs. Chip Enable (E) is the power

control and should be used for device selection.

Output Enable (G) is the output control and should

be used to gate data to the output pins,

independent of device selection. Assuming that

the addresses are stable, the address access time

-O

OUT

AI01823B

Test Condition

= 0V

OUT

= 0V

Min

Max

Unit

AVQV

) is equal to the delay from E to output

ELQV

). Data is available at the output after a delay

of t

GLQV

from the falling edge of G, assuming that

E has been low and the addresses have been

stable for at least t

AVQV

-t

GLQV

Standby Mode

The M27V402 has a standby mode which reduces

the supply current from 20mA to 20µA with low

voltage operation V

≤

3.6V, see Read Mode DC

Characteristics table for details. The M27V402 is

placed in the standby mode by applying a CMOS

high signal to the E input. When in the standby

mode, the outputs are in a high impedance state,

independent of the G input.

4/15

M27V402

Table 7. Read Mode DC Characteristics

(1)

(TA = 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; V

= 3.3V ± 10%; V

= V

)

Symbol

CC1

CC2

IH (2)

Output High Voltage CMOS

Parameter

Input Leakage Current

Output Leakage Current

Supply Current

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Program Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage TTL

= 2.1mA

= –400µA

= –100µA

2.4

–0.7V

Test Condition

≤

OUT

≤

E = V

, G = V

, I

OUT

= 0mA,

f = 5MHz, V

= 3.6V

E = V

E > V

– 0.2V, V

= 3.6V

= V

–0.3

Min

Max

±10

0.8

+ 1

0.4

Unit

µA

Note: 1. V

must be applied simultaneously with or before V

and removed simultaneously or after V

2. Maximum DC voltage on Output is V

+0.5V.

Two Line Output Control

Because EPROMs are usually used in larger

memory arrays, the product features a 2 line con-

trol function which accommodates the use of mul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control

lines, E should be decoded and used as the prima-

ry device selecting function, while G should be

made a common connection to all devices in the

array and connected to the READ line from the

system control bus. This ensures that all deselect-

ed memory devices are in their low power standby

mode and that the output pins are only active

when data is required from a particular memory

device.

-O

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupling of the

devices. The supply current, I

, has three seg-

ments that are of interest to the system designer:

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

the transient current peaks is dependent on the

output capacitive and inductive loading of the de-

vice.

The associated transient voltage peaks can be

suppressed by complying with the two line output

control and by properly selected decoupling ca-

pacitors. It is recommended that a 0.1µF ceramic

capacitor be used on every device between V

and V

. This should be a high frequency capaci-

tor of low inherent inductance and should be

placed as close to the device as possible. In addi-

tion, a 4.7µF bulk electrolytic capacitor should be

used between V

and V

for every eight devic-

es. The bulk capacitor should be located near the

power supply connection point.The purpose of the

bulk capacitor is to overcome the voltage drop

caused by the inductive effects of PCB traces.

5/15