M28F010
1024K (128K x 8) CMOS FLASH MEMORY
Y
Y
Y
Y
Y
Flash Electrical Chip-Erase
5 Second Typical
Quick-Pulse Programming Algorithm
10
ms
Typical Byte-Program
2 Second Typical Chip-Program
Single High Voltage for Writing and
Erasing
CMOS Low Power Consumption
30 mA Maximum Active Current
100
mA
Maximum Standby Current
Command Register Architecture for
Microprocessor Microcontroller
Compatible Write Interface
Noise Immunity Features
g
10% V
CC
Tolerance
Maximum Latch-Up Immunity
through EPI Processing
Y
Y
Y
Y
ETOX-III Flash-Memory Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Compatible with JEDEC-Standard
Byte-Wide EPROM Pinouts
10 000 Program Erase Cycles Minimum
Available in Three Product Grades
QML
b
55 C to
a
125 C (T
C
)
SE2
b
40 C to
a
125 C (T
C
)
SE3
b
40 C to
a
110 C (T
C
)
Y
Intel’s M28F010 is a 1024-Kbit byte-wide in-system re-writable CMOS nonvolatile flash memory It is orga-
nized as 131 072 bytes of 8 bits and is available in a 32-pin hermetic CERDIP package The M28F010 is also
available in 32-contact leadless chip carrier J-lead and Flatpack surface mount packages It offers the most
cost-effective and reliable alternative for updatable nonvolatile memory The M28F010 adds electrical chip-
erasure and reprogramming to EPROM technology Memory contents of the M28F010 can be erased and
reprogrammed 1) in a socket 2) in a PROM programmer socket 3) on-board during subassembly test 4) in-
system during final test and 5) in-system after-sale
The M28F010 increases memory flexibility while contributing to time- and cost-savings It is targeted for
alterable code- data-storage applications where traditional EEPROM functionality (byte erasure) is either not
required or is not cost-effective Use of the M28F010 is also appropriate where EPROM ultraviolet erasure is
impractical or too time consuming
271111– 1
Figure 1 M28F010 Block Diagram
January 1996
Order Number 271111-005
M28F010
271111 –3
271111 – 2
271111 –16
Figure 2 M28F010 Pin Configurations
Table 1 Pin Description
Symbol
A
0
–A
16
DQ
0
– DQ
7
Type
INPUT
INPUT OUTPUT
Name and Function
ADDRESS INPUTS
for memory addresses Addresses are internally
latched during a write cycle
DATA INPUT OUTPUT
Inputs data during memory write cycles
outputs data during memory read cycles The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled Data is internally latched during a write cycle
CHIP ENABLE
Activates the device’s control logic input buffers
decoders and sense amplifiers CE is active low CE high deselects the
memory device and reduces power consumption to standby levels
OUTPUT ENABLE
Gates the devices output through the data buffers
during a read cycle OE is active low
WRITE ENABLE
Controls writes to the control register and the array
Write enable is active low Addresses are latched on the falling edge
and data is latched on the rising edge of the WE pulse
Note
With V
PP
s
V
CC
a
2V memory contents cannot be altered
ERASE PROGRAM POWER SUPPLY
for writing the command
register erasing the entire array or programming bytes in the array
DEVICE POWER SUPPLY
(5V
g
10%)
GROUND
NO INTERNAL CONNECTION
to device Pin may be driven or left
floating
CE
INPUT
OE
WE
INPUT
INPUT
V
PP
V
CC
V
SS
NC
2
M28F010
271111 –4
Figure 3 M28F010 in a M80C186 System
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming The
M28F010 introduces a command register to manage
this new functionality The command register allows
for 100% TTL-level control inputs fixed power sup-
plies during erasure and programming and maxi-
mum EPROM compatibility
In the absence of high voltage on the V
PP
pin the
M28F010 is a read-only memory Manipulation of the
external memory-control pins yields the standard
EPROM read standby output disable and intelli-
gent Identifier operations
The same EPROM read standby and output disable
operations are available when high voltage is ap-
plied to the V
PP
pin In addition high voltage on V
PP
enables erasure and programming of the device All
functions associated with altering memory con-
tents intelligent Identifier erase erase verify pro-
gram and program verify are accessed via the
command register
Commands are written to the register using standard
microprocessor write timings Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry Write
cycles also internally latch addresses and data
needed for programming or erase operations With
the appropriate command written to the register
standard microprocessor read timings output array
data access the intelligent Identifier codes or out-
put data for erase and program verification
The command register is only alterable when V
PP
is
at high voltage Depending upon the application the
system designer may choose to make the V
PP
pow-
er supply switchable available only when memory
updates are desired When high voltage is removed
the contents of the register default to the read com-
mand making the M28F010 a read-only memory
Memory contents cannot be altered
3
M28F010
Table 2 M28F010 Bus Operations
Pins
Operation
Read
Output Disable
READ-ONLY
Standby
intelligent Identifier (Mfr)
(2)
intelligent Identifier (Device)
(2)
Read
READ WRITE
Output Disable
Standby
(4)
Write
V
PPL
V
PPL
V
PPL
V
PPL
V
PPL
V
PPH
V
PPH
V
PPH
V
PPH
A
0
X
X
V
IL
V
IH
A
0
X
X
A
0
A
9
X
X
V
ID(7)
V
ID(7)
A
9
X
X
A
9
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
V
IH
V
IL
V
IL
V
IH
X
V
IL
V
IL
V
IL
V
IH
X
V
IH
V
IH
V
IH
X
V
IH
V
IH
V
IH
V
IH
X
V
IL
Data Out
Tri-State
Tri-State
Data
e
89H
Data
e
B4H
Data Out
(3)
Tri-State
Tri-State
Data In
(5)
V
PP(1)
A
0
A
9
CE
OE
WE
DQ
0
– DQ
7
NOTES
1 V
PPL
may be ground a no-connect with a resistor tied to ground or as defined in the Characteristics Section V
PPH
is the
programming voltage specified for the device Refer to DC Characteristics When V
PP
e
V
PPL
memory contents can be
read but not written or erased
2 Manufacturer and device codes may also be accessed via a command register write sequence Refer to Table 3 All other
addresses low
3 Read operations with V
PP
e
V
PPH
may access array data or the intelligent Identifier codes
4 With V
PP
at high voltage the standby current equals I
CC
a
I
PP
(standby)
5 Refer to Table 3 for valid Data-In during a write operation
6 X can be V
IL
or V
IH
7 V
ID
is the intelligent Identifier high voltage Refer to DC Characteristics
Or the system designer may choose to ‘‘hardwire’’
V
PP
making the high voltage supply constantly
available In this instance all operations are per-
formed in conjunction with the command register
The M28F010 is designed to accommodate either
design practice and to encourage optimization of
the processor-memory interface
er supply switchable available only when memory
updates are desired When V
PP
e
V
PPL
the con-
tents of the register default to the read command
making the 28F010 a read-only memory In this
mode the memory contents cannot be altered
Or the system designer may choose to ‘‘hardwire’’
V
PP
making the high voltage supply constantly
available In this case all Command Register func-
tions are inhibited whenever V
CC
is below the write
lockout voltage V
LKO
(See Power Up Down Protec-
tion) The 28F010 is designed to accommodate ei-
ther design practice and to encourage optimization
of the processor-memory interface
BUS OPERATIONS
Read
The M28F010 has two control functions both of
which must be logically active to obtain data at the
outputs Chip-Enable (CE) is the power control and
should be used for device selection Output-Enable
(OE) is the output control and should be used
to gate data from the output pins independent of
device selection Figure 6 illustrates read timing
waveforms
Integrated Stop Timer
Sucessive command write cycles define the dura-
tions of program and erase operations specifically
the program or erase time durations are normally
terminated by associated program or erase verify
commands An integrated stop timer provides simpli-
fied timing control over these operations thus elimi-
nating the need for maximum program erase timing
specifications Programming and erase pulse dura-
tions are minimums only When the stop timer termi-
nates a program or erase operation the device
enters an inactive state and remains inactive until
receiving the appropriate verify or reset command
Write Protection
The command register is only active when V
PP
is at
high voltage Depending upon the application the
system designer may choose to make the V
PP
pow-
4
M28F010
When V
PP
is high (V
PPH
) the read operation can be
used to access array data to output the intelligent
Identifier codes and to access data for program
erase verification When V
PP
is low (V
PPL
) the read
operation can
only
access the array data
Output Disable
With Output-Enable at a logic-high level (V
IH
) output
from the device is disabled Output pins are placed
in a high-impedance state
Standby
With Chip-Enable at a logic-high level the standby
operation disables most of the M28F010’s circuitry
and substantially reduces device power consump-
tion The outputs are placed in a high-impedance
state independent of the Output-Enable signal
If the M28F010 is deselected during erasure pro-
gramming or program erase verification the
device draws active current until the operation is
terminated
intelligent Identifier Operation
The intelligent Identifier operation outputs the manu-
facturer code (89H) and device code (B4H) Pro-
gramming equipment automatically matches the de-
vice with its proper erase and programming algo-
rithms
With Chip-Enable and Output-Enable at a logic low
level raising A9 to high voltage V
ID
activates the
operation Data read from locations 0000H and
0001H represent the manufacturer’s code and the
device code respectively
The manufacturer- and device-codes can also be
read via the command register for instances where
the M28F010 is erased and reprogrammed in the
target system Following a write of 90H to the com-
mand register a read from address location 0000H
outputs the manufacturer code (89H) A read from
address 0001H outputs the device code (B4H)
Write
Device erasure and programming are accomplished
via the command register when high voltage is ap-
plied to the V
PP
pin The contents of the register
serve as input to the internal state-machine The
state-machine outputs dictate the function of the
device
The command register itself does not occupy an ad-
dressable memory location The register is a latch
used to store the command along with address and
data information needed to execute the command
The command register is written by bringing Write-
Enable to a logic-low level (V
IL
) while Chip-Enable is
low Addresses are latched on the falling edge of
Write-Enable while data is latched on the rising
edge of the Write-Enable pulse Standard microproc-
essor write timings are used
The three high-order register bits (R7 R6 R5) en-
code the control functions All other register bits R4
to R0 must be zero The only exception is the reset
command when FFH is written to the register Reg-
ister bits R7 – R0 correspond to data inputs D7 – D0
Refer to AC Write Characteristics and the Erase
Programming Waveforms for specific timing
parameters
5
