M28W160BT
M28W160BB
16 Mbit (1Mb x16, Boot Block) Low Voltage Flash Memory
PRELIMINARY DATA
s
SUPPLY VOLTAGE
– V
DD
= 2.7V to 3.6V: for Program, Erase and
Read
– V
DDQ
= 1.65V or 2.7V: Input/Output option
– V
PP
= 12V: optional Supply Voltage for fast
Program
µBGA
s
ACCESS TIME
– 2.7V to 3.6V: 90ns
– 2.7V to 3.6V: 100ns
s
PROGRAMMING TIME:
– 10µs typical
– Double Word Programming Option
TSOP48 (N)
12 x 20mm
µBGA46 (GB)
8 x 6 solder balls
s
s
PROGRAM/ERASE CONTROLLER (P/E.C.)
COMMON FLASH INTERFACE
– 64 bit Security Code
MEMORY BLOCKS
– Parameter Blocks (Top or Bottom location)
– Main Blocks
Figure 1. Logic Diagram
s
s
BLOCK PROTECTION on TWO PARAMETER
BLOCKS
– WP for Block Protection
20
A0-A19
W
E
G
RP
WP
VDD VDDQ VPP
16
DQ0-DQ15
s
s
s
AUTOMATIC STAND-BY MODE
PROGRAM and ERASE SUSPEND
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS of DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M28W160BT: 90h
– Bottom Device Code, M28W160BB: 91h
s
M28W160BT
M28W160BB
s
VSS
AI02628
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/39
M28W160BT, M28W160BB
Figure 2. µBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A13
A11
A8
VPP
WP
A19
A7
A4
B
A14
A10
W
RP
A18
A17
A5
A2
C
A15
A12
A9
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI02629
Figure 3. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
VPP
WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
A16
VDDQ
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
Table 1. Signal Names
A0-A19
DQ0-DQ7
DQ8-DQ15
E
G
W
RP
WP
V
DD
V
DDQ
V
PP
V
SS
NC
Address Inputs
Data Input/Output, Command Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Reset
Write Protect
Supply Voltage
Power Supply for
Input/Output Buffers
Optional Supply Voltage for
Fast Program & Erase
Ground
Not Connected Internally
12 M28W160BT 37
13 M28W160BB 36
24
25
AI02630
2/39
M28W160BT, M28W160BB
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO
V
DD
, V
DDQ
V
PP
Parameter
Ambient Operating Temperature
(2)
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Program Voltage
Value
–40 to 85
–40 to 125
–55 to 155
–0.6 to V
DDQ
+0.6
–0.6 to 4.1
–0.6 to 13
Unit
°C
°C
°C
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Depends on range.
DESCRIPTION
The M28W160B is a 16 Mbit non-volatile Flash
memory that can be erased electrically at the block
level and programmed in-system on a Word-by-
Word basis. The device is offered in the TSOP48
(10 x 20mm) and the µBGA46, 0.75mm ball pitch
packages. When shipped, all bits of the
M28W160B are in the ‘1’ state.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Each block can be programmed and
erased over 100,000 cycles. V
DDQ
allows to drive
the I/O pin down to 1.65V. An optional 12V V
PP
power supply is provided to speed up the program
phase at customer production line environment.
An internal Command Interface (C.I.) decodes the
instructions to access/modify the memory content.
The Program/Erase Controller (P/E.C.) automati-
cally executes the algorithms taking care of the
timings necessary for program and erase opera-
tions. Verification is performed too, unburdening
the microcontroller, while the Status Register
tracks the status of the operation.
The following instructions are executed by the
M28W160B: Read Array, Read Electronic Signa-
ture, Read Status Register, Clear Status Register,
Program, Double Word Program, Block Erase,
Program/Erase Suspend, Program/Erase Re-
sume and CFI Query.
Organisation
The M28W160B is organised as 1 Mbit by 16 bits.
A0-A19 are the address lines; DQ0-DQ15 are the
Data Input/Output. Memory control is provided by
Chip Enable E, Output Enable G and Write Enable
W inputs. The Program and Erase operations are
managed automatically by the P/E.C. Block pro-
tection against Program or Erase provides addi-
tional data security.
The upper two (or lower two) parameter blocks
can be protected to secure the code content of the
memory. WP controls protection and unprotection
operations.
Memory Blocks
The device features an asymmetrical blocked ar-
chitecture. The M28W160B has an array of 39
blocks: 8 Parameter Blocks of 4 KWord and 31
Main Blocks of 32 KWord. M28W160BT has the
Parameter Blocks at the top of the memory ad-
dress space while the M28W160BB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Tables 3 and 4.
The two upper parameter block can be protected
from accidental programming or erasure using
WP. Each block can be erased separately. Erase
can be suspended in order to perform either read
or program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed.
3/39
M28W160BT, M28W160BB
Table 3. Top Boot Block Addresses,
M28W160BT
#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Size
(KWord)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Address Range
FF000-FFFFF
FE000-FEFFF
FD000-FDFFF
FC000-FCFFF
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
Table 4. Bottom Boot Block Addresses,
M28W160BB
#
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Size
(KWord)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
Address Range
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
4/39
M28W160BT, M28W160BB
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A19).
The address signals
are inputs driven with CMOS voltage levels. They
are latched during a write operation.
Data Input/Output (DQ0-DQ15).
The data in-
puts, a word to be programmed or a command to
the C.I., are latched on the Chip Enable E or Write
Enable W rising edge, whichever occurs first. The
data output from the memory Array, the Electronic
Signature or Status Register is valid when Chip
Enable E and Output Enable G are active. The
output is high impedance when the chip is dese-
lected, the outputs are disabled or RP is tied to V
IL
.
Commands are issued on DQ0-DQ7.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E at V
IH
deselects
the memory and reduces the power consumption
to the stand-by level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at V
IL
.
Output Enable (G).
The Output Enable controls
the data Input/Output buffers.
Write Enable (W).
This input controls writing to
the Command Register, Input Address and Data
latches.
Write Protect (WP).
Write Protect is an input to
protect or unprotect the two lockable parameter
blocks. When WP is at V
IL
, the lockable blocks are
protected. Program or erase operations are not
achievable. When WP is at V
IH
, the lockable
blocks are unprotected and they can be pro-
grammed or erased (refer to Table 9).
Reset Input (RP).
The RP input provides hard-
ware reset of the memory. When RP is at V
IL
, the
memory is in reset mode: the outputs are put to
High-Z and the current consumption is minimised.
When RP is at V
IH
, the device is in normal opera-
tion. Exiting reset mode the device enters read ar-
ray mode.
V
DD
Supply Voltage (2.7V to 3.6V).
V
DD
pro-
vides the power supply to the internal core of the
memory device. It is the main power supply for all
operations (Read, Program and Erase). It ranges
from 2.7V to 3.6V.
V
DDQ
Supply Voltage (1.65V to V
DD
).
V
DDQ
provides the power supply to the I/O pins and en-
ables all Outputs to be powered independently
from V
DD
. V
DDQ
can be tied to V
DD
or it can use a
separate supply. It can be powered either from
1.65V to 2.2V or from 2.7V to 3.6V.
V
PP
Program Supply Voltage (12V).
V
PP
is
both a control input and a power supply pin. The
two functions are selected by the voltage range
applied to the pin.
If V
PP
is kept in a low voltage range (0V to 3.6V)
V
PP
is seen as a control input. In this case a volt-
age lower than V
PPLK
gives an absolute protection
against program or erase, while V
PP
> V
PP1
en-
ables these functions. V
PP
value is only sampled
at the beginning of a program or erase; a change
in its value after the operation has been started
does not have any effect and program or erase are
carried on regularly.
If V
PP
is used in the range 11.4V to 12.6V acts as
a power supply pin. In this condition V
PP
value
must be stable until P/E algorithm is completed
(see Table 22 and 23).
V
SS
Ground.
V
SS
is the reference for all the volt-
age measurements.
5/39
