M29F105B
1 Mbit (64Kb x16, Block Erase) Single Supply Flash Memory
5V±10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 55ns
FAST PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Word-by-Word
– Status Register bits
MEMORY BLOCKS
– Boot Block (Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 0087h
TSOP40 (N)
10 x 14mm
Figure 1. Logic Diagram
VCC
16
A0-A15
16
DQ0-DQ15
Table 1. Signal Names
A0-A15
DQ0-DQ7
DQ8-DQ15
E
G
W
V
CC
V
SS
Address Inputs
Data Input/Outputs, Command Inputs
Data Input/Outputs
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
W
E
G
M29F105B
VSS
AI02115
May 1998
1/28
M29F105B
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO
(2)
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
Value
–40 to 85
–50 to 125
–65 to 150
–0.6 to 7
–0.6 to 7
–0.6 to 13.5
Unit
°
C
°
C
°
C
V
V
V
V
CC
V
(A9, E, G)
(2)
A9, E, G Voltage
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
Figure 2. TSOP Pin Connections
DESCRIPTION
The M29F105B is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Word-by-Word basis
using only a single 5V V
CC
supply. Word program-
ming takes typically 20µs. For Program and Erase
operations the necessary high voltages are gener-
ated internally. The device can also be pro-
grammed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment
and in the application.They can also be temporarily
unprotected. Each block can be programmed and
erased over 100,000 cycles.
Block erase is performed in typically 1.0 second for
the main blocks.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume Block Protect and Blocks
Unprotect are written to the device in cycles of
commands to a Command Interface using stand-
ard microprocessor write timings.
The device is offered in TSOP40 (10 x 14mm)
packages.
Organisation
The M29F105B is organised as 64K x16 bits. The
memory uses the address inputs A0-A15 and the
Data Input/OutputsDQ0-DQ15. Memory control is
provided by Chip Enable E, Output Enable G and
Write Enable W inputs.
A0
A1
A2
A3
A4
A5
A6
A7
A8
VSS
A9
A10
A11
A12
A13
A14
A15
NC
W
VCC
1
40
10
11
M29F105B
31
30
20
21
AI02116
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC
E
Warning:
NC = Not Connected.
2/28
M29F105B
Figure 3. Memory Map and Block Address Table
M29F105B
FFFFh
32K WORD MAIN BLOCK
8000h
7FFFh
16K WORD MAIN BLOCK
4000h
3FFFh
3000h
2FFFh
2000h
1FFFh
8K WORD BOOT BLOCK
0000h
AI02117
4K WORD PARAMETER BLOCK
4K WORD PARAMETER BLOCK
Table 3. M29F105B Block Address Table
Address Range
0000h-1FFFh
2000h-2FFFh
3000h-3FFFh
4000h-7FFFh
8000h-FFFFh
A15
0
0
0
0
1
A14
0
0
0
1
X
A13
0
1
1
X
X
A12
X
0
1
X
X
Erase and Program operations are controlled by an
internal Program/Erase Controller (P/E.C.). Status
Register data output on DQ7 provides a Data Poll-
ing signal, and DQ6 and DQ2 provide Toggle
signals to indicate the state of the P/E.C opera-
tions.
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. The
M29F105B device has an array of 5 blocks, one
Boot Block of 8K Words, two Parameter Blocks of
4K Words, one Main Block of 16K Words and one
Main Blocks of 32K Words. The M29F105B locates
the Boot Block starting at thebottom of the memory
address space. The memory map is shown in
Figure 3. Each block can be erased separately, any
combination of blocks can be specified for multi-
block erase or the entire chip may be erased. The
Erase operations are managed automatically by
the P/E.C. The block erase operation can be sus-
pended in order to read from or program to any
block not being erased, and then resumed. Block
protection provides additional data security. Each
block can be separately protected or unprotected
against Program or Erase on programming equip-
ment.
Bus Operations
The following operations can be performed using
the appropriatebus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
tection, Unprotection, Protection Verify and
Unprotection Verify. See Tables.
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/EraseController
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
3/28
M29F105B
Instructions
Ten instructions are definedto perform Read Array,
Auto Select (to read the Electronic Signature or
Block Protection Status), Program, Block Protect,
Blocks Unprotect, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. The internal P/E.C.
automatically handles all timing and verification of
the Program and Erase operations. The Status
Register Data Polling, Toggle and Error bits may be
read at any time, during programming or erase, to
monitor the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interfacewhich iscommon to all instruc-
tions (see Table 9). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection,the instruc-
tions for Program and Block or Chip Erase require
further command inputs. For a Programinstruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the command con-
firmation on the sixth cycle. Erasure of a memory
block may be suspended,in orderto read data from
another block or to program data in another block,
and then resumed.
The Block Protect and Blocks Unprotect com-
mands allow these operations to be performed in
the application. They provide a six cycle command
access of the equivalent bus operations. This en-
ables updates of the memory protected blocks in
the field, without the use of a programmer or the
need to generate 12V on the application.
When power is first applied or if V
CC
falls below
V
LKO
, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A15).
The address inputs for
the memory array are latched during a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. When A9 is raised to V
ID
, either a Read
ElectronicSignature Manufactureror Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1 A6, A12 and A15.
Data Input/Outputs (DQ0-DQ15).
The input is
data to be programmed in the memory array or a
command to be written to the C.I. Both are latched
on the rising edge of Chip EnableE or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputs are disabled and when RPNC is at a Low
level.
Chip Enable (E).
The Chip Enable input activates
the memory control logic, input buffers, decoders
and sense amplifiers. E High deselectsthe memory
and reduces the power consumptionto the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to V
ID
during the Block Unprotection opera-
tion.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V
ID
level during
Block Protection and Unprotection operations.
Write Enable (W).
This input controls writing to the
Command Registerand Addressand Datalatches.
V
CC
Supply Voltage.
The power supply for all
operations (Read, Program and Erase).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
DEVICE OPERATIONS
See Tables 4, 5 and 6.
Read.
Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
Write.
Write operations are used to give Instruction
Commands to the memory or to latch input data to
be programmed. A write operation is initiated when
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whichever occurs last.
Commands and Input Dataare latchedon therising
edge of W or E whichever occurs first.
Output Disable.
The data outputs are high imped-
ance when the Output Enable G is High with Write
Enable W High.
Standby.
The memory is in standby when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
4/28
M29F105B
Table 4. User Bus Operations
(1)
Operation
Read Word
Write Word
Output Disable
Standby
Reset
Block
Protection
(2)
Blocks
Unprotection
Block
Protection
Verify
(2,4)
Block
Unprotection
(2,4)
Verify
Notes:
1.
2.
3.
4.
E
V
IL
V
IL
V
IL
V
IH
X
V
IL
V
ID
G
V
IL
V
IH
V
IH
X
X
V
ID
V
ID
W
V
IH
V
IL
V
IH
X
X
V
IL
Pulse
V
IL
Pulse
A0
A0
A0
X
X
X
X
X
A1
A1
A1
X
X
X
X
X
A6
A6
A6
X
X
X
X
X
A9
A9
A9
X
X
X
V
ID
V
ID
A12
A12
A12
X
X
X
X
V
IH
A15
A15
A15
X
X
X
X
V
IH
DQ0-DQ15
Data Output
Data Input
Hi-Z
Hi-Z
Hi-Z
X
X
Block Protect
Status
(3)
Block Protect
Status
(3)
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
V
ID
A12
A15
V
IL
V
IL
V
IH
V
IL
V
IH
V
IH
V
ID
A12
A15
X = V
IL
or V
IH
Block Address must be given on A12-A15 bits.
See Table 6.
Operation performed on programming equipment.
Table 5. Read Electronic Signature (following AS instruction or with A9 = V
ID
)
Code
Manufact. Code
Device Code
E
V
IL
V
IL
G
V
IL
V
IL
W
V
IH
V
IH
A0
V
IL
V
IH
A1
V
IL
V
IL
Other
Addresses
Don’t Care
Don’t Care
DQ8-DQ15
00h
00h
DQ0-DQ7
20h
87h
Table 6. Read Block Protection with AS Instruction
Code
Protected Block
Unprotected Block
E
V
IL
V
IL
G
V
IL
V
IL
W
V
IH
V
IH
A0
V
IL
V
IL
A1
V
IH
V
IH
A12-A15
Block Address
Block Address
Other
Addresses
Don’t Care
Don’t Care
DQ0-DQ7
01h
00h
Automatic Standby.
After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumptionis reduced to the CMOS
standby value, while outputs still drive the bus.
Electronic Signature.
Two codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for STMi-
croelectronics is 20h,the device code is 87h. These
codes allow programming equipment or applica-
tions to automatically match their interface to the
characteristics of the M29F105B. The Electronic
Signature is output by a Read operation when the
voltage applied to A9 is at V
ID
and address inputs
A1 is Low. The manufacturer code is output when
the Address input A0 is Low and the device code
when this input is High. Other Address inputs are
ignored. The codes are output on DQ0-DQ7. This
is shown in Table 4.
The Electronic Signature can also be read, without
raising A9 to V
ID
, by giving the memory the Instruc-
tion AS. The codes are output on DQ0-DQ7 with
DQ8-DQ15 at 00h.
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