M29F800AT
M29F800AB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
Single Supply Flash Memory
s
SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
ACCESS TIME: 70ns
PROGRAMMING TIME
– 8µs per Byte/Word typical
19 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 16 Main Blocks
1
44
s
s
s
s
PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
TSOP48 (N)
12 x 20mm
SO44 (M)
s
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
Figure 1. Logic Diagram
s
TEMPORARY BLOCK UNPROTECTION
MODE
LOW POWER CONSUMPTION
– Standby and Automatic Standby
19
A0-A18
W
E
G
RP
VCC
s
15
DQ0-DQ14
DQ15A–1
M29F800AT
M29F800AB
BYTE
RB
s
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29F800AT: 00ECh
– Bottom Device Code M29F800AB: 0058h
s
s
VSS
AI02198B
July 2000
1/22
M29F800AT, M29F800AB
Figure 2. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
Figure 3. SO Connections
12
13
M29F800AT
M29F800AB
37
36
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11 M29F800AT 34
12 M29F800AB 33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
24
21
22
23
AI02101B
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
24
25
AI02199
Table 1. Signal Names
A0-A18
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
G
W
RP
RB
BYTE
V
CC
V
SS
NC
2/22
Address Inputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
Ground
Not Connected Internally
SUMMARY DESCRIPTION
The M29F800A is an 8 Mbit (1Mb x8 or 512Kb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single 5V supply. On power-up the
memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
M29F800AT, M29F800AB
Table 2. Absolute Maximum Ratings
(1)
Symbol
Parameter
Ambient Operating Temperature (Temperature Range Option 1)
T
A
Ambient Operating Temperature (Temperature Range Option 6)
Ambient Operating Temperature (Temperature Range Option 3)
T
BIAS
T
STG
V
IO (2)
V
CC
V
ID
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Identification Voltage
Value
0 to 70
–40 to 85
–40 to 125
–50 to 125
–65 to 150
–0.6 to 6
–0.6 to 6
–0.6 to 13.5
Unit
°C
°C
°C
°C
°C
V
V
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
The blocks in the memory are asymmetrically ar-
ranged, see Tables 3 and 4, Block Addresses. The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be
used for small initialization code to start the micro-
processor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).
3/22
M29F800AT, M29F800AB
Table 3. Top Boot Block Addresses,
M29F800AT
#
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Size
(Kbytes)
16
8
8
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Address Range
(x8)
FC000h-FFFFFh
FA000h-FBFFFh
F8000h-F9FFFh
F0000h-F7FFFh
E0000h-EFFFFh
D0000h-DFFFFh
C0000h-CFFFFh
B0000h-BFFFFh
A0000h-AFFFFh
90000h-9FFFFh
80000h-8FFFFh
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
Address Range
(x16)
7E000h-7FFFFh
7D000h-7DFFFh
7C000h-7CFFFh
78000h-7BFFFh
70000h-77FFFh
68000h-6FFFFh
60000h-67FFFh
58000h-5FFFFh
50000h-57FFFh
48000h-4FFFFh
40000h-47FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
00000h-07FFFh
Table 4. Bottom Boot Block Addresses,
M29F800AB
#
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Size
(Kbytes)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
8
8
16
Address Range
(x8)
F0000h-FFFFFh
E0000h-EFFFFh
D0000h-DFFFFh
C0000h-CFFFFh
B0000h-BFFFFh
A0000h-AFFFFh
90000h-9FFFFh
80000h-8FFFFh
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
Address Range
(x16)
78000h-7FFFF h
70000h-77FFFh
68000h-6FFFF h
60000h-67FFFh
58000h-5FFFF h
50000h-57FFFh
48000h-4FFFF h
40000h-47FFFh
38000h-3FFFF h
30000h-37FFFh
28000h-2FFFF h
20000h-27FFFh
18000h-1FFFF h
10000h-17FFFh
08000h-0FFFF h
04000h-07FFFh
03000h-03FFFh
02000h-02FFFh
00000h-01FFFh
4/22
M29F800AT, M29F800AB
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A18).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, V
IH
. When BYTE is Low, V
IL
, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, V
IH
, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
IL
, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP).
The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See the Ready/Busy
Output section, Table 17 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
ID
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 17 and Figure
11, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V
OL
. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE).
The Byte/
Word Organization Select pin is used to switch be-
tween the 8-bit and 16-bit Bus modes of the mem-
ory. When Byte/Word Organization Select is Low,
V
IL
, the memory is in 8-bit mode, when it is High,
V
IH
, the memory is in 16-bit mode.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC4
.
V
SS
Ground.
The V
SS
Ground is the reference for
all voltage measurements.
5/22
