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M29W102BT

M29W102BB

1 Mbit (64Kb x16, Boot Block)

Low Voltage Single Supply Flash Memory

SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 50ns

PROGRAMMING TIME

– 10µs per Word typical

5 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location)

– 2 Parameter and 2 Main Blocks

PROGRAM/ERASE CONTROLLER

– Embedded Word Program algorithm

– Embedded Multi-Block/Chip Erase algorithm

– Status Register Polling and Toggle Bits

TSOP40 (N)

10 x 14mm

ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

Figure 1. Logic Diagram

UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

VCC

TEMPORARY BLOCK UNPROTECTION

MODE

LOW POWER CONSUMPTION

– Standby and Automatic Standby

100,000 PROGRAM/ERASE CYCLES per

BLOCK

M28F102 COMPATIBLE

– Pin-out and Read Mode

20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h

– Top Device Code M29W102BT: 0099h

– Bottom Device Code M29W102BB: 0098h

A0-A15

DQ0-DQ15

M29W102BT

M29W102BB

VSS

AI02785

March 2000

1/20

M29W102BT, M29W102BB

Figure 2. TSOP Connections

SUMMARY DESCRIPTION

The M29W102B is a 1 Mbit (64Kb x16) non-vola-

tile memory that can be read, erased and repro-

grammed. These operations can be performed

using a single low voltage (2.7 to 3.6V) supply. On

power-up the memory defaults to its Read mode

where it can be read in the same way as a ROM or

EPROM.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

The blocks in the memory are asymmetrically ar-

ranged, see Tables 3 and 4, Block Addresses. The

first or last 32 Kwords have been divided into four

additional blocks. The 8 Kword Boot Block can be

used for small initialization code to start the micro-

processor, the two 4 Kword Parameter Blocks can

be used for parameter storage and the remaining

16 Kwords are a small Main Block where the appli-

cation may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in a TSOP40 (10 x 14mm)

package and it is supplied with all the bits erased

(set to ’1’).

A10

A11

A12

A13

A14

A15

VCC

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

10 M29W102BT 31

11 M29W102BB 30

AI02786

VSS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VSS

Table 1. Signal Names

A0-A15

DQ0-DQ15

Address Inputs

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Supply Voltage

Ground

Not Connected Internally

2/20

M29W102BT, M29W102BB

Table 2. Absolute Maximum Ratings

(1)

Symbol

Ambient Operating Temperature (Temperature Range Option 6)

BIAS

STG

IO (2)

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Supply Voltage

Identification Voltage

–40 to 85

–50 to 125

–65 to 150

–0.6 to 4

–0.6 to 13.5

°C

Parameter

Ambient Operating Temperature (Temperature Range Option 1)

Value

0 to 70

Unit

°C

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Table 3. Top Boot Block Addresses

M29W102BT

Size

(KWords)

Address Range

E000h-FFFFh

D000h-DFFFh

C000h-CFFFh

8000h-BFFFh

0000h-7FFFh

Table 4. Bottom Boot Block Addresses

M29W102BB

Size

(KWords)

Address Range

8000h-FFFFh

4000h-7FFFh

3000h-3FFFh

2000h-2FFFh

0000h-1FFFh

3/20

M29W102BT, M29W102BB

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A15).

The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ15).

The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations DQ0-DQ7 represent the com-

mands sent to the Command Interface of the inter-

nal state machine; the Command Interface does

not use DQ8-DQ15 to decode the commands.

Chip Enable (E).

The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, V

, all other pins are ignored.

Output Enable (G).

The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W).

The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Reset/Block Temporary Unprotect (RP).

The Re-

set/Block Temporary Unprotect pin can be used to

apply a Hardware Reset to the memory or to tem-

porarily unprotect all blocks that have been pro-

tected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, V

, for at least

PLPX

. After Reset/Block Temporary Unprotect

goes High, V

, the memory will be ready for Bus

Read and Bus Write operations after t

PHEL

or t

PLYH

, whichever occurs last. See Table 15 and

Figure 10, Reset/Temporary Unprotect AC Char-

acteristics for more details.

Holding RP at V

will temporarily unprotect the

protected blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from V

to V

must be slower than

PHPHH

Reset/Block Temporary Unprotect can be left un-

connected. A weak internal pull-up resistor en-

sures that the memory always operates correctly.

Supply Voltage.

The V

Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the Lockout Voltage,

LKO

. This prevents Bus Write operations from ac-

cidentally damaging the data during power-up,

power-down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the V

Supply Voltage pin and the V

Ground

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, I

CC3

Ground.

The V

Ground is the reference for

all voltage measurements.

4/20

M29W102BT, M29W102BB

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Table 5, Bus Operations, for a summary. Typically

glitches of less than 5ns on Chip Enable or Write

Enable are ignored by the memory and do not af-

fect bus operations.

Bus Read.

Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, V

, to Chip Enable

and Output Enable and keeping Write Enable

High, V

. The Data Inputs/Outputs will output the

value, see Figure 7, Read Mode AC Waveforms,

and Table 12, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write.

Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

able must remain High, V

, during the whole Bus

Write operation. See Figures 8 and 9, Write AC

Waveforms, and Tables 13 and 14, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable.

The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, V

Standby.

When Chip Enable is High, V

, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

Table 5. Bus Operations

Operation

Bus Read

Bus Write

Output Disable

Standby

Read Manufacturer

Code

Read Device Code

Note: X = V

or V

ance state. To reduce the Supply Current to the

Standby Supply Current, I

CC2

, Chip Enable should

be held within V

± 0.2V. For the Standby current

level see Table 11, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, I

CC3

, for Program or Erase operations un-

til the operation completes.

Automatic Standby.

If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, I

CC2

. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

They require V

to be applied to some pins.

Electronic Signature.

The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These codes can be read by applying the signals

listed in Table 5, Bus Operations.

Block Protection

and

Blocks Unprotection.

Each

block can be separately protected against acci-

dental Program or Erase. Protected blocks can be

unprotected to allow data to be changed.

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. For further information refer to Application

Note AN1122, Applying Protection and Unprotec-

tion to M29 Series Flash.

Address Inputs

Cell Address

Command Address

A0 = V

, A1 = V

, A9 = V

Others V

or V

A0 = V

, A1 = V

, A9 = V

Others V

or V

Data

Inputs/Outputs

Data Output

Data Input

Hi-Z

0020h

0099h (M29W102BT)

0098h (M29W102BB)

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