M29W160BT
M29W160BB
16 Mbit (2Mb x8 or 1Mb x16, Boot Block)
Low Voltage Single Supply Flash Memory
PRELIMINARY DATA
s
SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
ACCESS TIME: 70ns
PROGRAMMING TIME
– 10µs per Byte/Word typical
35 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 32 Main Blocks
TSOP48 (N)
12 x 20mm
1
44
s
s
s
SO44 (M)
s
PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
LFBGA48 (ZA)
8 x 6 solder balls
FBGA
s
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
Figure 1. Logic Diagram
s
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
TEMPORARY BLOCK UNPROTECTION
MODE
SECURITY MEMORY BLOCK
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
A0-A19
W
E
G
RP
M29W160BT
M29W160BB
20
15
DQ0-DQ14
DQ15A–1
BYTE
RB
VCC
s
s
s
s
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W160BT: 22C4h
– Bottom Device Code M29W160BB: 2249h
s
s
VSS
AI00981
Note: RB not available on SO44 package.
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/24
M29W160BT, M29W160BB
Figure 2. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
W
RP
NC
NC
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
Figure 3. SO Connections
12 M29W160BT 37
13 M29W160BB 36
RP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11 M29W160BT 34
12 M29W160BB 33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
24
21
22
23
AI00978
W
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
24
25
AI02994
Table 1. Signal Names
A0-A19
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
G
W
RP
RB
BYTE
V
CC
V
SS
NC
DU
2/24
Address Inputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
(Not available on SO44 package)
Byte/Word Organization Select
Supply Voltage
Ground
Not Connected Internally
Don’t Use as internally connected
SUMMARY DESCRIPTION
The M29W160B is a 16 Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
M29W160BT, M29W160BB
Figure 4. LFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
F
A13
A12
A14
A15
A16
BYTE
DQ15
A–1
VSS
E
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
D
W
RP
DU
A19
DQ5
DQ12
VCC
DQ4
C
RB
DU
A18
DU
DQ2
DQ10
DQ11
DQ3
B
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A
A3
A4
A2
A1
A0
E
G
VSS
AI02985B
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Tables 3 and 4, Block Addresses. The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be
used for small initialization code to start the micro-
processor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm),
SO44 and LFBGA48 (0.8mm pitch) packages. Ac-
cess times of 70ns, 90ns and 120ns are available.
The memory is supplied with all the bits erased
(set to ’1’).
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, V
IH
. When BYTE is Low, V
IL
, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
3/24
M29W160BT, M29W160BB
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
Ambient Operating Temperature (Temperature Range Option 6)
T
BIAS
T
STG
V
IO (2)
V
CC
V
ID
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Identification Voltage
–40 to 85
–50 to 125
–65 to 150
–0.6 to 4
–0.6 to 4
–0.6 to 13.5
Parameter
Ambient Operating Temperature (Temperature Range Option 1)
Value
0 to 70
Unit
°C
°C
°C
°C
V
V
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, V
IH
, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
IL
, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP).
The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See the Ready/Busy
Output section, Table 18 and Figure 12, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
ID
will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 18 and Figure
12, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V
OL
. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE).
The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se-
lect is Low, V
IL
, the memory is in 8-bit mode, when
it is High, V
IH
, the memory is in 16-bit mode.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
4/24
M29W160BT, M29W160BB
Table 3. Top Boot Block Addresses,
M29W160BT
#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Size
(Kbytes)
16
8
8
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Address Range
(x8)
1FC000h-1FFFFFh
1FA000h-1FBFFFh
1F8000h-1F9FFFh
1F0000h-1F7FFFh
1E0000h-1EFFFFh
1D0000h-1DFFFFh
1C0000h-1CFFFFh
1B0000h-1BFFFFh
1A0000h-1AFFFFh
190000h-19FFFFh
180000h-18FFFFh
170000h-17FFFFh
160000h-16FFFFh
150000h-15FFFFh
140000h-14FFFFh
130000h-13FFFFh
120000h-12FFFFh
110000h-11FFFFh
100000h-10FFFFh
0F0000h-0FFFFFh
0E0000h-0EFFFFh
0D0000h-0DFFFFh
0C0000h-0CFFFFh
0B0000h-0BFFFFh
0A0000h-0AFFFFh
090000h-09FFFFh
080000h-08FFFFh
070000h-07FFFFh
060000h-06FFFFh
050000h-05FFFFh
040000h-04FFFFh
030000h-03FFFFh
020000h-02FFFFh
010000h-01FFFFh
000000h-00FFFFh
Address Range
(x16)
FE000h-FFFFF h
FD000h-FDFFFh
FC000h-FCFFFh
F8000h-FBFFFh
F0000h-F7FFFh
E8000h-EFFFFh
E0000h-E7FFFh
D8000h-DFFFFh
D0000h-D7FFFh
C8000h-CFFFFh
C0000h-C7FFFh
B8000h-BFFFFh
B0000h-B7FFFh
A8000h-AFFFFh
A0000h-A7FFFh
98000h-9FFFFh
90000h-97FFFh
88000h-8FFFFh
80000h-87FFFh
78000h-7FFFFh
70000h-77FFFh
68000h-6FFFFh
60000h-67FFFh
58000h-5FFFFh
50000h-57FFFh
48000h-4FFFFh
40000h-47FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
00000h-07FFFh
Table 4. Bottom Boot Block Addresses,
M29W160BB
#
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Size
(Kbytes)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
8
8
16
Address Range
(x8)
1F0000h-1FFFFFh
1E0000h-1EFFFFh
1D0000h-1DFFFFh
1C0000h-1CFFFFh
1B0000h-1BFFFFh
1A0000h-1AFFFFh
190000h-19FFFFh
180000h-18FFFFh
170000h-17FFFFh
160000h-16FFFFh
150000h-15FFFFh
140000h-14FFFFh
130000h-13FFFFh
120000h-12FFFFh
110000h-11FFFFh
100000h-10FFFFh
0F0000h-0FFFFFh
0E0000h-0EFFFFh
0D0000h-0DFFFFh
0C0000h-0CFFFFh
0B0000h-0BFFFFh
0A0000h-0AFFFFh
090000h-09FFFFh
080000h-08FFFFh
070000h-07FFFFh
060000h-06FFFFh
050000h-05FFFFh
040000h-04FFFFh
030000h-03FFFFh
020000h-02FFFFh
010000h-01FFFFh
008000h-00FFFFh
006000h-007FFFh
004000h-005FFFh
000000h-003FFFh
Address Range
(x16)
F8000h-FFFFFh
F0000h-F7FFFh
E8000h-EFFFFh
E0000h-E7FFFh
D8000h-DFFFF h
D0000h-D7FFFh
C8000h-CFFFF h
C0000h-C7FFFh
B8000h-BFFFFh
B0000h-B7FFFh
A8000h-AFFFFh
A0000h-A7FFFh
98000h-9FFFF h
90000h-97FFFh
88000h-8FFFF h
80000h-87FFFh
78000h-7FFFF h
70000h-77FFFh
68000h-6FFFF h
60000h-67FFFh
58000h-5FFFF h
50000h-57FFFh
48000h-4FFFF h
40000h-47FFFh
38000h-3FFFF h
30000h-37FFFh
28000h-2FFFF h
20000h-27FFFh
18000h-1FFFF h
10000h-17FFFh
08000h-0FFFF h
04000h-07FFFh
03000h-03FFFh
02000h-02FFFh
00000h-01FFFh
5/24
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