M29W512B
512 Kbit (64Kb x8, Bulk)
Low Voltage Single Supply Flash Memory
s
SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
ACCESS TIME: 55ns
PROGRAMMING TIME
– 10µs per Byte typical
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Chip Erase algorithm
– Status Register Polling and Toggle Bits
TSOP32 (NZ)
8 x 14mm
PLCC32 (K)
s
s
s
s
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
LOW POWER CONSUMPTION
– Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES
20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 27h
VCC
s
s
s
Figure 1. Logic Diagram
s
16
A0-A15
W
E
G
M29W512B
8
DQ0-DQ7
VSS
AI02743
March 2000
1/18
M29W512B
Figure 2. TSOP Connections
Figure 3. PLCC Connections
A11
A9
A8
A13
A14
NC
W
VCC
NC
NC
A15
A12
A7
A6
A5
A4
A12
A15
NC
NC
VCC
W
NC
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
G
A10
E
DQ7
9
M29W512B
25
17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
AI02755
1
32
8
9
M29W512B
25
24
16
17
AI02976
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Table 1. Signal Names
A0-A15
DQ0-DQ7
E
G
W
V
CC
V
SS
NC
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
Not Connected Internally
SUMMARY DESCRIPTION
The M29W512B is a 512 Kbit (64Kb x8) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (2.7 to 3.6V) supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a program or erase operation can be detected and
any error conditions identified. The command set
required to control the memory is consistent with
JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP32 (8 x 14mm) and
PLCC32 packages and it is supplied with all the
bits erased (set to ’1’).
2/18
M29W512B
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
ID
Parameter
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Identification Voltage
Value
0 to 70
–50 to 125
–65 to 150
–0.6 to 4
–0.6 to 4
–0.6 to 13.5
Unit
°C
°C
°C
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A15).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power-up,
power-down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC3
.
Vss Ground.
The V
SS
Ground is the reference
for all voltage measurements.
3/18
M29W512B
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 3, Bus Operations, for a summary. Typically
glitches of less than 5ns are ignored by the mem-
ory and do not affect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
CC2
, Chip Enable should
be held within V
CC
± 0.2V. For the Standby current
level see Table 9, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC3
, for Program or Erase operations un-
til the operation completes.
Automatic Standby.
If CMOS levels (V
CC
± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V
ID
to be applied to some pins.
Electronic Signature.
The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 3, Bus Operations.
Table 3. Bus Operations
Operation
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Note: X = V
IL
or V
IH
.
E
V
IL
V
IL
X
V
IH
V
IL
V
IL
G
V
IL
V
IH
V
IH
X
V
IL
V
IL
W
V
IH
V
IL
V
IH
X
V
IH
V
IH
Address Inputs
Cell Address
Command Address
X
X
A0 = V
IL
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
A0 = V
IH
, A1 = V
IL
, A9 = V
ID
,
Others V
IL
or V
IH
Data
Inputs/Outputs
Data Output
Data Input
Hi-Z
Hi-Z
20h
27h
4/18
M29W512B
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The commands are summarized in Table 4, Com-
mands. Refer to Table 4 in conjunction with the
text descriptions below.
Read/Reset Command.
The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Chip Erase operation the memory will take about
10µs to abort the Chip Erase. During the abort pe-
riod no valid data can be read from the memory.
Issuing a Read/Reset command during a Chip
Erase operation will leave invalid data in the mem-
ory.
Auto Select Command.
The Auto Select com-
mand is used to read the Manufacturer Code and
the Device Code. Three consecutive Bus Write op-
erations are required to issue the Auto Select com-
mand. Once the Auto Select command is issued
the memory remains in Auto Select mode until an-
other command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
IL
and A1 = V
IL
. The other address bits
may be set to either V
IL
or V
IH
. The Manufacturer
Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read
operation with A0 = V
IH
and A1 = V
IL
. The other
address bits may be set to either V
IL
or V
IH
. The
Device Code for the M29W512B is 27h.
Program Command.
The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
Table 4. Commands
Command
Length
Bus Write Operations
1st
Addr
X
555
555
555
555
X
X
555
Data
F0
AA
AA
AA
AA
A0
90
AA
2AA
2AA
2AA
2AA
PA
X
2AA
55
55
55
55
PD
00
55
555
80
555
AA
2AA
55
555
10
X
555
555
555
F0
90
A0
20
PA
PD
2nd
Addr
Data
3rd
Addr
Data
4th
Addr
Data
5th
Addr
Data
6th
Addr
Data
1
Read/Reset
3
Auto Select
Program
Unlock Bypass
Unlock Bypass
Program
Unlock Bypass Reset
Chip Erase
3
4
3
2
2
6
Note: X Don’t Care, PA Program Address, PD Program Data.
All values in the table are in hexadecimal.
The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care.
Read/Reset.
After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select.
After an Auto Select command, read Manufacturer ID or Device ID.
Program, Unlock Bypass Program, Chip Erase.
After these commands read the Status Register until the Program/Erase Controller com-
pletes and the memory returns to Read Mode.
Unlock Bypass.
After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset.
After the Unlock Bypass Reset command read the memory as normal until another command is issued.
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