M29W800T
M29W800B
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory
NOT FOR NEW DESIGN
M29W800T and M29W800B are replaced
respectively by the M29W800AT and
M29W800AB
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 90ns
FAST PROGRAMMING TIME
– 10µs by Byte / 20µs by Word typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte or Word-by-Word
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code, M29W800T: 00D7h
– Device Code, M29W800B: 005Bh
DESCRIPTION
The M29W800 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byteor Word-
by-Word basis using only a single 2.7V to 3.6V V
CC
supply. For Program and Erase operations the
necessary high voltages are generated internally.
The device can also be programmed in standard
programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
June 1999
44
1
TSOP48 (N)
12 x 20 mm
SO44 (M)
Figure 1. Logic Diagram
VCC
19
A0-A18
W
E
G
RP
M29W800T
M29W800B
15
DQ0-DQ14
DQ15A–1
BYTE
RB
VSS
AI02178
1/33
This is information on a product still in production but not recommended for new designs.
M29W800T, M29W800B
Figure 2A. TSOP Pin Connections
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
Figure 2B. TSOP Reverse Pin Connections
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
1
48
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
12
13
M29W800T
M29W800B
(Normal)
37
36
12
13
M29W800T
M29W800B
(Reverse)
37
36
24
25
AI02179
24
25
AI02180
Warning:
NC = Not Connected.
Warning:
NC = Not Connected.
Figure 2C. SO Pin Connections
Table 1. Signal Names
A0-A18
Address Inputs
Data Input/Outputs, Command Inputs
Data Input/Outputs
Data Input/Output or Address Input
Chip Enable
Output Enable
Write Enable
Reset / Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organisation
Supply Voltage
Ground
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11 M29W800T
12 M29W800B
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
G
W
RP
RB
BYTE
V
CC
V
SS
AI02181
2/33
M29W800T, M29W800B
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
(A9, E, G, RP)
(2)
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
A9, E, G, RP Voltage
Value
–40 to 85
–50 to 125
–65 to 150
–0.6 to 5
–0.6 to 5
–0.6 to 13.5
Unit
°
C
°
C
°
C
V
V
V
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
DESCRIPTION
(Cont’d)
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written to the device in
cycles of commandsto a Command Interfaceusing
standard microprocessor write timings.
The device is offered in TSOP48 (12 x 20mm) and
SO44 packages. Both normal and reverse pinouts
are available for the TSOP48 package.
Organisation
The M29W800 is organised as 1 M x8 or 512K x16
bits selectable by the BYTE signal. When BYTE is
Low the Byte-wide x8 organisation is selected and
the address lines are DQ15A–1 and A0-A18. The
Data Input/Output signal DQ15A–1 acts as ad-
dress line A–1 which selects the lower or upper
Byte of the memory word for output on DQ0-DQ7,
DQ8-DQ14 remain at High impedan ce. When
BYTE is High the memory uses the address inputs
A0-A18 and the Data Input/Outputs DQ0-DQ15.
Memory control is provided by Chip Enable E,
Output Enable G and Write Enable W inputs.
AReset/Block TemporaryUnprotection RP tri-level
input provides a hardware reset when pulled Low,
and when held High (at V
ID
) temporarily unprotects
blocks previously protected allowing them to be
programed and erased. Erase and Program opera-
tions are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W800Tand M29W800Bdevices have an array
of 19 blocks, one Boot Block of 16 KBytes or 8
KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and fifteenMain Blocks of 64 KBytes or 32
KWords. The M29W800T has the Boot Block at the
top of the memory address space and the
M29W800B locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
3.
Each block can be erased separately, any combi-
nation of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the
P/E.C. The block erase operation can be sus-
pended in order to read from or program to any
block not being ersased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed using
the appropriatebus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
t ec t io n , Unp ro t e ct io n, P ro t e cti on Verif y,
Unprotection Verify and Block Temporary Unpro-
tection. See Tables 4 and 5.
3/33
M29W800T, M29W800B
Figure 3A. Top Boot Block Memory Map and Block Address Table
TOP BOOT BLOCK
Word-Wide
7FFFFh
78000h
77FFFh
70000h
6FFFFh
68000h
67FFFh
60000h
5FFFFh
58000h
57FFFh
50000h
4FFFFh
48000h
47FFFh
40000h
3FFFFh
38000h
37FFFh
30000h
2FFFFh
28000h
27FFFh
20000h
1FFFFh
18000h
17FFFh
10000h
0FFFFh
08000h
07FFFh
00000h
Byte-Wide
FFFFFh
16K BOOT BLOCK
F0000h
EFFFFh
64K MAIN BLOCK
E0000h
DFFFFh
64K MAIN BLOCK
D0000h
CFFFFh
64K MAIN BLOCK
C0000h
BFFFFh
64K MAIN BLOCK
B0000h
AFFFFh
64K MAIN BLOCK
A0000h
9FFFFh
64K MAIN BLOCK
90000h
8FFFFh
64K MAIN BLOCK
80000h
7FFFFh
64K MAIN BLOCK
70000h
6FFFFh
64K MAIN BLOCK
60000h
5FFFFh
64K MAIN BLOCK
50000h
4FFFFh
64K MAIN BLOCK
40000h
3FFFFh
64K MAIN BLOCK
30000h
2FFFFh
64K MAIN BLOCK
20000h
1FFFFh
64K MAIN BLOCK
10000h
0FFFFh
64K MAIN BLOCK
00000h
AI01725B
Byte-Wide
FFFFFh
FC000h
FBFFFh
8K PARAMETER BLOCK
FA000h
F9FFFh
8K PARAMETER BLOCK
F8000h
F7FFFh
32K MAIN BLOCK
F0000h
Word-Wide
7FFFFh
7E000h
7DFFFh
7D000h
7CFFFh
7C000h
7BFFFh
78000h
4/33
M29W800T, M29W800B
Figure 3B. Bottom Boot Block Memory Map and Block Address Table
BOTTOM BOOT BLOCK
Word-Wide
7FFFFh
78000h
77FFFh
70000h
6FFFFh
68000h
67FFFh
60000h
5FFFFh
58000h
57FFFh
50000h
4FFFFh
48000h
47FFFh
40000h
3FFFFh
38000h
37FFFh
30000h
2FFFFh
28000h
27FFFh
20000h
1FFFFh
18000h
17FFFh
10000h
0FFFFh
08000h
07FFFh
00000h
Byte-Wide
FFFFFh
64K MAIN BLOCK
F0000h
EFFFFh
64K MAIN BLOCK
E0000h
DFFFFh
64K MAIN BLOCK
D0000h
CFFFFh
64K MAIN BLOCK
C0000h
BFFFFh
64K MAIN BLOCK
B0000h
AFFFFh
64K MAIN BLOCK
A0000h
9FFFFh
64K MAIN BLOCK
90000h
8FFFFh
64K MAIN BLOCK
80000h
7FFFFh
64K MAIN BLOCK
70000h
6FFFFh
64K MAIN BLOCK
60000h
5FFFFh
64K MAIN BLOCK
50000h
4FFFFh
64K MAIN BLOCK
40000h
3FFFFh
64K MAIN BLOCK
30000h
2FFFFh
64K MAIN BLOCK
20000h
1FFFFh
64K MAIN BLOCK
10000h
0FFFFh
16K BOOT BLOCK
00000h
AI01731B
Byte-Wide
0FFFFh
32K MAIN BLOCK
08000h
07FFFh
8K PARAMETER BLOCK
06000h
05FFFh
8K PARAMETER BLOCK
04000h
03FFFh
00000h
Word-Wide
07FFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
00000h
5/33
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