PB0121 Product Brief
IGLOO2 FPGAs Product Brief
Microsemi IGLOO
®
2 FPGAs integrate fourth generation flash-based FPGA fabric and high-performance communications interfaces
on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable and highest security programmable logic solution.
This next generation IGLOO2 architecture offers up to 3.6X gate count implemented with 4-input look-up table (LUT) fabric with carry
chains, giving 2X performance, and includes multiple embedded memory options and mathblocks for digital signal processing (DSP).
High speed serial interfaces include PCI EXPRESS (PCIe), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer
(XGXS) plus native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers
provide high speed memory interfaces.
IGLOO2 Family
High-Performance FPGA
•
•
Efficient 4-Input LUTs with Carry Chains for
High-Performance and Low Power
Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large
SRAM) with 400 MHz Synchronous Performance (512 x
36, 512 x 32, 1 Kbit x 18, 1 Kbit x 16, 2 Kbit x 9, 2 Kbit x
8, 4 Kbit x 4, 8 Kbit x 2, or 16 Kbit x 1)
Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2
Read Ports and 1 Write Port (micro SRAM)
High-Performance DSP
–
Up to 240 Fast mathblocks with 18 x 18 Signed
Multiplication, 17 x 17 Unsigned Multiplication and
44-Bit Accumulator
•
High Speed Memory Interfaces
•
Up to 2 High Speed DDRx Memory Controllers
–
–
–
–
–
–
–
HPMS DDR (MDDR) and Fabric DDR (FDDR)
Controllers
Supports LPDDR/DDR2/DDR3
Maximum 333 MHz Clock Rate
SECDED Enable/Disable Feature
Supports Various DRAM Bus Width Modes, x8, x9,
x16, x18, x32, x36
Supports Command Reordering to Optimize Memory
Efficiency
Supports Data Reordering, Returning Critical Word
First for Each Command
•
•
High Speed Serial Interfaces
•
Up to 16 SERDES Lanes, Each Supporting:
–
–
XGXS/XAUI Extension (To Implement a 10 Gbps
(XGMII) Ethernet PHY Interface)
Native SERDES Interface Facilitates Implementation
of Serial RapidIO in Fabric or an SGMII Interface to a
soft Ethernet MAC
PCI Express (PCIe) Endpoint Controller
x1, x2, x4 Lane PCI Express Core
Up to 2 Kbytes Maximum Payload Size
64-/32-Bit AXI/AHB Master and Slave Interfaces
to the Application Layer
SDRAM Support through a Soft SDRAM Memory
Controller
64 KB Embedded SRAM (eSRAM)
Up to 512 KB Embedded Nonvolatile Memory (eNVM)
One SPI/COMM_BLK
DDR Bridge (2 Port Data R/W Buffering Bridge to DDR
Memory) with 64-Bit AXI Interface
Non-Blocking, Multi-Layer AHB Bus Matrix Allowing
Multi-Master Scheme Supporting 5 Masters and 7
Slaves
High-Performance Memory Subsystem
•
•
•
•
•
–
June 2016
© 2016 Microsemi Corporation
I
IGLOO2 FPGAs Product Brief
•
•
Two AHB/APB Interfaces to FPGA Fabric (Master/Slave
Capable)
Two DMA Controllers to Offload Data Transactions
–
•
8-Channel Peripheral DMA (PDMA) for Data
Transfer Between HPMS Peripherals and Memory
•
–
–
–
–
–
–
–
–
Supply-Chain Assurance Device Certificate
Enhanced Anti-Tamper Features
Zeroization
Non-Deterministic Random Bit Generator (NRBG)
User Cryptographic Services (AES-256, SHA-256,
Elliptical Curve Cryptographic (ECC) Engine)
User Physically Unclonable Function (PUF) Key
Enrollment and Regeneration
CRI Pass-Through DPA Patent Portfolio
License
Hardware Firewalls Protecting
Subsystem (HPMS) Memories
Microcontroller
Data Security Features (available on premium devices)
High-Performance DMA (HPDMA) for Data Transfer
Between eSRAM and DDR Memories
Clock Sources
–
–
–
High Precision 32 kHz to 20 MHz Main Crystal
Oscillator
1 MHz Embedded RC Oscillator
50 MHz Embedded RC Oscillator
•
•
Clocking Resources
•
•
Up to 8 Clock Conditioning Circuits (CCCs) with Up to 8
Integrated Analog PLLs
–
Output Clock with 8 Output Phases and 45° Phase
Difference (Multiply/Divide, and Delay Capabilities)
Reliability
Single Event Upset (SEU) Immune
–
Zero FIT FPGA Configuration Cells
Junction Temperature: 125°C – Military Temperature,
100°C – Industrial Temperature, 85°C – Commercial
Temperature
Single Error Correct Double Error Detect (SECDED)
Protection on the Following:
–
–
–
Embedded Memory (eSRAMs)
PCIe Buffer
DDR Memory Controllers with Optional SECDED
Modes
•
Frequency: Input 1 MHz to 200 MHz, Output 20 MHz to
400 MHz
1.2 V Core Voltage
Multi-Standard User I/Os (MSIO/MSIOD)
–
–
–
–
–
–
LVTTL/LVCMOS 3.3 V (MSIO only)
LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V
DDR (SSTL2_1, SSTL2_2)
LVDS, MLVDS,
Standards
PCI
LVPECL (receiver only)
DDR, DDR2, DDR3, LPDDR, SSTL2, SSTL18,
HSTL
LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V
Mini-LVDS,
RSDS
Differential
Operating Voltage and I/Os
•
•
•
•
Buffers Implemented with SEU Resistant Latches on the
Following:
–
–
DDR Bridges (HPMS, MDDR, FDDR)
SPI FIFO
•
DDR I/Os (DDRIO)
–
–
•
•
NVM Integrity Check at Power-Up and On-Demand
No External Configuration Memory Required—
Instant-On, Retains Configuration When Powered Off
Low Static and Dynamic Power
–
Flash*Freeze Mode for Fabric
Power as low as 13 mW/Gbps per lane for SERDES
devices
Up to 25% lower total power than competing devices
Low Power
•
•
•
•
•
Market Leading Number of User I/Os with 5G SERDES
Design Security Features (available on all devices)
–
Intellectual Property (IP) Protection through Unique
Security Features and Use Models New to the PLD
Industry
Encrypted User Key and Bitstream Loading,
Enabling Programming in Less-Trusted Locations
Security
–
II
R evis i o n 13
IGLOO2 FPGAs Product Brief
IGLOO2 FPGA Block Diagram
Acronyms
AES
AHB
APB
AXI
COMM_BLK
DDR
DPA
ECC
EDAC
FDDR
FIC
Advanced Encryption Standard
Advanced High-Performance Bus
Advanced Peripheral Bus
Advanced eXtensible Interface
Communication Block
Double Data Rate
Differential Power Analysis
Elliptical Curve Cryptography
Error Detection And Correction
DDR2/3 Controller in FPGA Fabric
Fabric Interface Controller
HPMS
IAP
MACC
MDDR
SECDED
SEU
SHA
XAUI
XGMII
XGXS
High-Performance Memory Subsystem
In-Application Programming
Multiply-Accumulate
DDR2/3 Controller in HPMS
Single Error Correct Double Error Detect
Single Event Upset
Secure Hashing Algorithm
10 Gbps Attachment Unit Interface
10 Gigabit Media Independent Interface
XGMII Extended Sublayer
R ev i si o n 1 3
III
IGLOO2 FPGAs Product Brief
Table 1 • IGLOO2 FPGA Product Family
Features
2, 3
Maximum Logic
Elements
(4LUT + DFF)
1
Math Blocks
(18x18)
PLLs and CCCs
SPI/HPDMA/PDMA
Fabric Interface
Controllers (FICs)
Data Security
eNVM (K Bytes)
Memory
LSRAM 18K Blocks
uSRAM1K Blocks
eSRAM (K Bytes)
Total RAM (K bits)
DDR Controllers
High
Speed
SERDES Lanes (T)
PCIe End Points
MSIO (3.3 V)
User I/Os
MSIOD (2.5 V)
DDRIO (2.5 V)
Total User I/O
Commercial (C),
Industrial (I), Military
(M), Automotive
(T1/T2)
0
0
119
28
66
209
123
40
70
233
703
912
1x18
4
1
157
40
70
267
139
62
176
377
1104
128
10
11
21
22
31
34
1
AES256, SHA256, RNG
256
69
72
64
1826
2x36
8
1826
1x18
4
2
271
40
76
387
309
40
76
425
2586
1x18
4
5000
2x36
16
4
292
106
176
574
69
72
109
112
M2GL005 (S)
6,060
M2GL010 (S/T/TS)
12,084
M2GL025 (T/TS)
27,696
M2GL050 (T/TS)
56,340
M2GL060 (T/TS)
56,520
M2GL090 (T/TS)
86,184
M2GL150 (T/TS)
146,124
Logic/DSP
11
2
22
34
72
6
1 each
2
72
84
240
8
1
AES256, SHA256, RNG, ECC, PUF
512
2
236
240
Grades
C, I, T1, T2
C, I, M, T1, T2
C, I, M
Notes:
1. Total logic may vary based on utilization of DSP and memories in your design. See the
UG0445: IGLOO2 FPGA and
SmartFusion2 SoC FPGA Fabric User Guide
for details.
2. Feature availability is package dependent.
3. Data security features are only available in "S" and "TS" devices.
IV
Revision 13
IGLOO2 FPGAs Product Brief
I/Os Per Package
Table 2 • I/Os per Package and Package Options
Package Options
4
Type
Pitch (mm)
Length x Width (mm)
Device
M2GL005 (S)
M2GL010 (T/TS)
1, 6
M2GL025 (T/TS)
1
M2GL050 (T/TS)
1
M2GL060 (T/TS)
1
M2GL090 (T/TS)
1, 2, 7
M2GL150 (T/TS)
2
I/O
FCS(G)325
5
0.5
11x11
Lanes
I/O
161
VF(G)256
5, 9
0.8
14x14
Lanes
-
I/O
FCS(G)536
5
0.5
16x16
Lanes
I/O
VF(G)400
5, 9
0.8
17x17
Lanes
I/O
FCV(G)484
5, 9
0.8
19x19
Lanes
I/O
84
84
TQ(G)144
5, 11
0.5
20x20
Lanes
-
-
I/O
FG(G)484
5, 10
1.0
23x23
Lanes
I/O
FG(G)676
5, 9
1.0
27x27
Lanes
I/O
FG(G)896
5
1.0
31x31
Lanes
I/O
FC(G)1152
5
1.0
35x35
Lanes
171
195
207
207
207
-
4
4
4
4
209
233
267
267
267
267
-
4
4
4
4
4
387
425
4
4
574
16
37
7
8
138
180
200
200
180
2
2
2
2
2
4
138
293
4
248
4
Notes:
1. Mil Temp 010/025/050/060/090 devices are only available in the FG(G)484 package.
2. Mil Temp 150 devices are only available in the FC(G)1152 package.
3. 090 FCS(G)325 is 11x13.5 pkg dimension.
4. All the packages mentioned above are available with lead and lead free.
5. (G) indicates that the package is RoHS 6/6 Compliant/Pb-free
6. M2GL010 (S) device is only available in TQ(G)144 package. M2GL010 (T/TS) devices are not available in TQ(G)144 package.
7. The M2GL090 (T/TS) device in the FCSG325 package is available with an ordering code of XZ48. The XZ48 ordering code
pre-configures the device for Auto Update mode. Minimum Order quantities apply, contact your local Microsemi sales office for
details.
8. Shaded cells indicate that the device packages have vertical migration capability.
9. Automotive T2 grade devices are available in the VF(G)256, VF(G)400, FG(G)484, and FG(G)676 packages.
10. Automotive T1 grade devices are available in the FG(G)484 package.
11. The TQ(G)144 package will be available in T2 grade by the end of February, 2017.
Table 3 • Features per Device/Package Combination
Package
TQ(G)144
8
Devices
MDDR
5G
5
Crystal
PCIe
SERDES
FDDR Oscillators Lanes
Endpoints
MSIO
(3.3V
max)
6
MSIOD
(2.5V
max)
7
DDRIO
(2.5V
max)
Total User
I/O
M2GL005 (S)
M2GL010 (S)
-
-
-
x18
1
x18
1
x18
1
x18
2
x18
1
x18
1
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
-
-
-
2
2
2
2
4
4
-
-
-
1
1
1
1
2
2
52
50
119
66
66
94
90
114
104
9
11
12
8
8
22
22
22
12
23
23
30
64
64
64
88
64
64
84
84
161
138
138
180
200
200
180
VF(G)256
8
M2GL005 (S)
M2GL010 (T/TS)
M2GL025 (T/TS)
FCS(G)325
8
M2GL025 (T/TS)
M2GL050 (T/TS)
M2GL060 (T/TS)
M2GL090 (T/TS)
R ev i si o n 1 3
V
