M16C/62P Group (M16C/62P, M16C/62PT)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0001-0241
Rev.2.41
Jan 10, 2006
1.
Overview
The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin
plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level
of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing
capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-
speed arithmetic/logic operations.
1.1
Applications
Audio, cameras, television, home appliance, office/communications/portable/industrial equipment, automobile,
etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 1 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
1.2
Performance Outline
Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version).
Table 1.1
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version)
Item
CPU
Number of Basic Instructions
Minimum Instruction Execution
Time
Operating Mode
Address Space
Memory Capacity
Peripheral
Function
Port
Multifunction Timer
Performance
M16C/62P
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip, memory expansion and microprocessor mode
1 Mbyte (Available to 4 Mbytes by memory space expansion
function)
See
Table 1.4 to 1.5 Product List
Input/Output : 113 pins, Input : 1 pin
Timer A : 16 bits x 5 channels,
Timer B : 16 bits x 6 channels,
Three phase motor control circuit
3 channels
Clock synchronous, UART, I
2
C bus
(1)
, IEBus
(2)
2 channels
Clock synchronous
10-bit A/D converter: 1 circuit, 26 channels
8 bits x 2 channels
2 channels
CCITT-CRC
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Stop detection of main clock oscillation, re-oscillation detection
function
Available (option
(4)
)
VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7µA (VCC1=VCC2=3V, stop mode)
3.3±0.3 V or 5.0±0.5 V
100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1)
(3)
-20 to 85°C,
-40 to 85°C
(3)
128-pin plastic mold LQFP
Serial Interface
A/D Converter
D/A Converter
DMAC
CRC Calculation Circuit
Watchdog Timer
Interrupt
Clock Generation Circuit
Electric
Characteristics
Oscillation Stop Detection
Function
Voltage Detection Circuit
Supply Voltage
Power Consumption
Flash memory
version
Program/Erase Supply Voltage
Program and Erase Endurance
Operating Ambient Temperature
Package
NOTES:
1. I
2
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See
Table 1.8 Product Code
for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 2 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.2
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version)
Item
Performance
M16C/62P
M16C/62PT
(4)
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip, memory expansion
Single-chip
and microprocessor mode
CPU
Number of Basic Instructions
Minimum Instruction
Execution Time
Operating Mode
Address Space
1 Mbyte (Available to 4 Mbytes by 1 Mbyte
memory space expansion function)
Memory Capacity
See
Table 1.4 to 1.7 Product List
Peripheral
Port
Input/Output : 87 pins, Input : 1 pin
Function
Multifunction Timer
Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface
3 channels
Clock synchronous, UART, I
2
C bus
(1)
, IEBus
(2)
2 channels
Clock synchronous
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
D/A Converter
8 bits x 2 channels
DMAC
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels
Interrupt
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Stop detection of main clock oscillation, re-oscillation detection function
Detection Function
Absent
Voltage Detection Circuit Available (option
(5)
)
Electric
Supply Voltage
VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1=VCC2=4.0 to 5.5V
Characteristics
VCC1 (f(BCLK=24MHz)
(f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
Power Consumption
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0µA (VCC1=VCC2=5V, f(XCIN)=32kHz,
wait mode)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz,
wait mode)
0.8µA (VCC1=VCC2=5V, stop mode)
0.7µA (VCC1=VCC2=3V, stop mode)
Flash memory Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V
5.0±0.5 V
version
Program and Erase
100 times (all area)
Endurance
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1)
(3)
Operating Ambient Temperature
-20 to 85°C,
T version : -40 to 85°C
V version : -40 to 125°C
-40 to 85°C
(3)
Package
100-pin plastic mold QFP, LQFP
NOTES:
1. I
2
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See
Table 1.8 and 1.9 Product Code
for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. Use the M16C/62PT on VCC1=VCC2
5. All options are on request basis.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 3 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.3
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version)
Item
Performance
M16C/62P
M16C/62PT
(4)
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip mode
CPU
1 Mbyte
Memory Capacity
See
Table 1.4 to 1.7 Product List
Peripheral
Port
Input/Output : 70 pins, Input : 1 pin
Function
Multifunction Timer
Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer),
Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial Interface
2 channels
Clock synchronous, UART, I
2
C bus
(1)
, IEBus
(2)
1 channel
Clock synchronous, I
2
C bus
(1)
, IEBus
(2)
2 channels
Clock synchronous (1 channel is only transmission)
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
D/A Converter
8 bits x 2 channels
DMAC
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels
Interrupt
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Stop detection of main clock oscillation, re-oscillation detection function
Detection Function
Absent
Voltage Detection Circuit Available (option
(4)
)
Electric
Supply Voltage
VCC1=3.0 to 5.5 V, (f(BCLK=24MHz)
VCC1=4.0 to 5.5V, (f(BCLK=24MHz)
Characteristics
VCC1=2.7 to 5.5 V, (f(BCLK=10MHz)
Power Consumption
14 mA (VCC1=5V, f(BCLK)=24MHz)
14 mA (VCC1=5V, f(BCLK)=24MHz)
8 mA (VCC1=3V, f(BCLK)=10MHz)
2.0µA (VCC1=5V, f(XCIN)=32kHz,
wait mode)
1.8µA (VCC1=3V, f(XCIN)=32kHz,
0.8µA (VCC1=5V, stop mode)
wait mode)
0.7µA (VCC1=3V, stop mode)
5.0 ± 0.5V
Flash memory Program/Erase Supply Voltage 3.3 ± 0.3V or 5.0 ± 0.5V
version
Program and Erase
100 times (all area)
Endurance
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1)
(3)
Operating Ambient Temperature
-20 to 85°C,
T version : -40 to 85°C
(3)
V version : -40 to 125°C
-40 to 85°C
Package
80-pin plastic mold QFP
NOTES:
1. I
2
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See
Table 1.8 and 1.9 Product Code
for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Number of Basic Instructions
Minimum Instruction
Execution Time
Operating Mode
Address Space
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 4 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
1.3
Block Diagram
Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram,
Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
<VCC1 ports>
(4)
Port P7
<VCC2 ports>
(4)
Internal peripheral functions
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
8
A/D converter
(10 bits
X
8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Port P8
7
(8 bits
X
3 channels)
CRC arithmetic circuit (CCITT )
(Polynomial : X
16
+X
12
+X
5
+1)
<VCC1 ports>
(4)
Port P8_5
Clock synchronous serial I/O
(8 bits
X
2 channels)
M16C/60 series16-bit CPU core
Watchdog timer
(15 bits)
R0H
R1H
R2
R3
A0
A1
FB
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
Memory
ROM
(1)
Port P9
8
DMAC
(2 channels)
RAM
(2)
Port P10
D/A converter
(8 bits X 2 channels)
8
Multiplier
<VCC1 ports>
(4)
Port P11
(3)
<VCC2 ports>
(4)
Port P12
(3)
Port P14
(3)
Port P13
(3)
8
2
8
8
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Figure 1.1
M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 5 of 96
