M16C/62 Group (M16C/62P, M16C/62PT)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0001-0210Z
Rev.2.10
Nov. 07, 2003
1. Overview
The M16C/62 group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high-per-
formance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin,
100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated
instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are ca-
pable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and
DMAC which combined with fast instruction processing capability, makes it suitable for control of various
OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations.
1.1 Applications
Audio, cameras, office/communications/portable/industrial equipment, automobile, etc
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.2.10 Nov. 07, 2003 page 1
of 84
M16C/62 Group (M16C/62P, M16C/62PT)
1. Overview
1.2 Performance Outline
Table 1.1 to table 1.3 list performance outline of M16C/62 group (M16C/62P, M16C/62PT).
Table 1.1 Performance outline of M16C/62 group (M16C/62P) (128-pin version)
Item
CPU
Number of basic instructions
Shortest instruction execution time
Operation mode
Memory space
Memory capacity
Port
Multifunction timer
Serial I/O
Performance
M16C/62P
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip, memory expansion and microprocessor mode
1 Mbyte (Available to 4M bytes by memory space
expansion function)
See
table 1.4 and 1.5 Product List
Input/Output : 113 pins, Input : 1 pin
Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels
Three phase motor control circuit
3 channels
Clock synchronous, UART,
I
2
C bus
(1)
, IEBus
(2)
2 channels
Clock synchronous
10-bit A-D converter: 1 circuit, 26 channels
8 bits x 2 channels
2 channels
CCITT-CRC
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
Ring oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Stop detection of main clock oscillation
,
re-oscillation detection
function
Available (option
(4)
)
VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=24MHz)
VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8
µA
(VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7
µ
A (VCC1=VCC2=3V, stop mode)
3.3
±
0.3 V or 5.0
±
0.5 V
100 times (all area)
or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)
(3)
–20 to 85
o
C
–40 to 85
o
C
(3)
128-pin plastic mold QFP
Peripheral
function
A-D converter
D-A converter
DMAC
CRC calculation circuit
Watchdog timer
Interrupt
Clock generating circuit
Oscillation stop detection function
Voltage detection circuit
Supply voltage
Power consumption
Electric
characteris-
tics
Flash memory
Version
Program/erase supply voltage
Program and erase endurance
Operating ambient temperature
Package
NOTES:
1. I
2
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See
table 1.8 Product Code
for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule.
4. All options are on request basis.
Rev.2.10 Nov. 07, 2003 page 2
of 84
M16C/62 Group (M16C/62P, M16C/62PT)
Table 1.2 Performance outline of M16C/62 group (M16C/62P, M16C/62PT) (100-pin version)
Item
M16C/62P
CPU
Performance
1. Overview
M16C/62PT
(Note 4)
Number of basic instructions 91 instructions
Shortest instruction execution time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operation mode
Single-chip, memory expansion and Single-chip mode
microprocessor mode
Memory space
1 Mbyte (Available to 4 Mbytes by 1M byte
memory space expansion function)
Memory capacity
See
table 1.4 to 1.7 Product List
Port
Input/Output : 87 pins, Input : 1pin
Peripheral
Multifunction timer
Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels
function
Three phase motor control circuit
Serial I/O
3 channels
Clock synchronous, UART,
I
2
C bus
(1)
, IEBus
(2)
2 channels
Clock synchronous
A-D converter
10-bit A-D converter: 1 circuit, 26 channels
D-A converter
8 bits x 2 channels
DMAC
2 channels
CRC calculation circuit
CCITT-CRC
Watchdog timer
15 bits x 1 channel (with prescaler)
Interrupt
Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
Clock generating circuit
4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
Ring oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation stop detection function Stop detection of main clock oscillation, re-oscillation detection function
Voltage detection circuit
Available (option
(5)
)
Absent
VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 VCC1=VCC2=4.0V to 5.5 V
Supply voltage
Electric
(f(BCLK)=24MHz)
(f(BCLK)=24MHz)
characteris-
VCC1=2.7 to 5.5V, V
CC2
=2.7V to VCC1
tics
(f(BCLK)=10MHz)
Power consumption
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0
µA
(VCC1=VCC2=5V,
1.8
µA
(VCC1=VCC2=3V,
f(XCIN)=32kHz, wait mode)
f(XCIN)=32kHz, wait mode)
0.8
µ
A (VCC1=VCC2=5V, stop mode)
0.7
µ
A (VCC1=VCC2=3V, stop mode)
3.3
±
0.3 V or 5.0
±
0.5 V
5.0
±
0.5 V
Flash memory Program/erase supply voltage
Program and erase endurance
100 times (all area)
Version
or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)
(3)
Operating ambient temperature
–20 to 85
o
C
T version : –40 to 85
o
C
–40 to 85
o
C
(3)
V version : –40 to 125
o
C
Package
100-pin plastic mold QFP, LQFP
NOTES:
1. I
2
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See
table 1.8 Product Code
for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule.
4. Use the high reliability version on VCC1 = VCC2.
5. All options are on request basis.
Rev.2.10 Nov. 07, 2003 page 3
of 84
M16C/62 Group (M16C/62P, M16C/62PT)
Table 1.3 Performance outline of M16C/62 group (M16C/62P, M16C/62PT) (80-pin version)
Item
M16C/62P
CPU
Performance
M16C/62PT
1. Overview
Number of basic instructions 91 instructions
Shortest instruction execution time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operation mode
Single-chip mode
Memory space
1M byte
Memory capacity
See table
1.4 to 1.7 Product List
Peripheral
Port
Input/Output : 70 pins, Input : 1pin
function
Multifunction timer
Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer)
Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial I/O
2 channels
Clock synchronous, UART,
I
2
C bus
(1)
, IEBus
(2)
1 channel
Clock synchronous,
2
C bus
(1)
, IEBus
(2)
I
2 channels
Clock synchronous (1 channel is only for transmission)
A-D converter
10-bit A-D converter: 1 circuit, 26 channels
D-A converter
8 bits x 2 channels
DMAC
2 channels
CRC calculation circuit
CCITT-CRC
Watchdog timer
15 bits x 1 channel (with prescaler)
Interrupt
Internal: 29 sources, External: 5 sources, Software: 4 sources,
Priority level: 7 levels
Clock generating circuit
4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
Ring oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation stop detection function Stop detection of main clock oscillation, re-oscillation detection function
Voltage detection circuit
Available (option
(4)
)
Absent
Electric
VCC1=3.0 to 5.5V, (f(BCLK)=24MHz) VCC1=4.0 to 5.5V, (f(BCLK)=24MHz)
Supply voltage
characteris-
VCC1=2.7 to 5.5V, (f(BCLK)=10MHz)
tics
Power consumption
14 mA (VCC1=5V, f(BCLK)=24MHz) 14 mA (VCC1=5V, f(BCLK)=24MHz)
8 mA (VCC1=3V, f(BCLK)=10MHz) 2.0
µA
(VCC1=5V,
1.8
µA
(VCC1=3V,
f(XCIN)=32kHz, wait mode)
f(XCIN)=32kHz, wait mode)
0.8
µ
A (VCC1=5V, stop mode)
0.7
µ
A (VCC1=3V, stop mode)
Flash
Program/erase supply voltage 3.3
±
0.3 V or 5.0
±
0.5 V
5.0
±
0.5 V
memory
Program and erase endurance
100 times (all area)
Version
or 1,000 times (user ROM area without block 1)
/ 10,000 times (block A, block 1)
(3)
Operating ambient temperature
–20 to 85
o
C
T version : –40 to 85
o
C
–40 to 85
o
C(option)
V version : –40 to 125
o
C
Package
80-pin plastic mold QFP
NOTES :
1. I
2
C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See
table 1.8 Product Code
for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule.
4. All options are on request basis.
Rev.2.10 Nov. 07, 2003 page 4
of 84
M16C/62 Group (M16C/62P, M16C/62PT)
1. Overview
1.3 Block Diagram
Figure 1.1 is a block diagram of the M16C/62 group (M16C/62P, M16C/62PT) 128-pin and 100-pin version,
figure 1.2 is a block diagram of the M16C/62 group (M16C/62P, M16C/62PT) 80-pin version.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
<VCC1 ports>
(4)
Port P7
<VCC2 ports>
(4)
Internal peripheral functions
8
A-D converter
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
(10 bits
X
8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
Ring oscillator
Clock synchronous serial I/O
Port P8
7
(8 bits
X
3 channels)
CRC arithmetic circuit (CCITT )
(Polynomial : X
16
+X
12
+X
5
+1)
<VCC1 ports>
(4)
Port P8_5
(8 bits
X
2 channels)
M16C/60 series16-bit CPU core
Watchdog timer
(15 bits)
R0H
R1H
R2
R3
A0
A1
FB
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
Memory
ROM
(1)
RAM
(2)
Port P9
8
DMAC
(2 channels)
Port P10
D-A converter
(8 bits X 2 channels)
8
Multiplier
<VCC1 ports>
(4)
Port P11
(3)
<VCC2 ports>
(4)
Port P12
(3)
Port P14
(3)
Port P13
(3)
8
2
8
8
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Figure 1.1 M16C/62 Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
Rev.2.10 Nov. 07, 2003 page 5
of 84
