Under development
This document is under development and its contents are subject to change
M16C/6N Group (M16C/6NK, M16C/6NM)
Renesas MCU
REJ03B0058-0210
Rev.2.10
Aug 25, 2006
1. Overview
The M16C/6N Group (M16C/6NK, M16C/6NM) of MCUs are built using the high-performance silicon gate
CMOS process using the M16C/60 Series CPU core and are packaged in 100-pin and 128-pin plastic
molded LQFP. These MCUs operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Being
equipped with two CAN (Controller Area Network) modules in the M16C/6N Group (M16C/6NK, M16C/6NM),
the MCU is suited to drive automotive and industrial control systems. The CAN modules comply with the 2.0B
specification. In addition, this MCU contains a multiplier and DMAC which combined with fast instruction
processing capability, makes it suitable for control of various OA, communication equipment which requires
high-speed arithmetic/logic operations.
1.1 Applications
• Car audio and industrial control systems, other (Normal-ver. product)
• Automotive, industrial control systems and other automobile, other (T/V-ver. product)
Specifications written in this manual are believed to be accurate, but are not
guaranteed to be entirely free of error. Specifications in this manual may be
changed for functional or performance improvements. Please make sure your
manual is the latest edition.
Rev.2.10 Aug 25, 2006
REJ03B0058-0210
page 1 of 81
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
1.2 Performance Overview
Tables 1.1 and 1.2 list the Functions and Specifications for M16C/6N Group (M16C/6NK, M16C/6NM).
Table 1.1 Functions and Specifications for M16C/6N Group (100-pin Version: M16C/6NK)
Specification
Item
Normal-ver.
T/V-ver.
CPU
Number of fundamental
91 instructions
instructions
Minimum instruction
41.7 ns (f(BCLK) = 24 MHz,
50.0 ns (f(BCLK) = 20 MHz,
execution time
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Operating mode
Single-chip, memory expansion, Single-chip mode
and microprocessor modes
Address space
1 Mbyte
Memory capacity
Refer to
Table 1.3 Product Information
Peripheral Ports
Input/Output: 87 pins, Input: 1 pin
Function
Multifunction timers
Timer A: 16 bits
✕
5 channels
Timer B: 16 bits
✕
6 channels
Three-phase motor control circuit
Serial interfaces
3 channels
Clock synchronous, UART, I
2
C-bus
(1)
, IEBus
(2)
2 channels
Clock synchronous
A/D converter
10-bit A/D converter: 1 circuit, 26 channels
D/A converter
8 bits
✕
2 channels
DMAC
2 channels
CRC calculation circuit
CRC-CCITT
CAN module
2 channels with 2.0B specification
Watchdog timer
15 bits
✕
1 channel (with prescaler)
Interrupts
Internal: 32 sources, External: 9 sources
Software: 4 sources, Priority levels: 7 levels
Clock generation circuits 4 circuits
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function
Electrical
Supply voltage
VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,
Characteristics
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Consumption Mask ROM 21 mA (f(BCLK) = 24 MHz,
-
current
PLL operation, no division)
Flash memory 23 mA (f(BCLK) = 24 MHz,
21 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
PLL operation, no division)
Mask ROM 3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
Flash memory 0.8 µA (Stop mode, Topr = 25°C)
Flash Memory Programming and erasure voltage 3.0 ± 0.3 V or 5.0 ± 0.5 V
5.0 ± 0.5 V
Version
Programming and erasure endurance 100 times
I/O
I/O withstand voltage
5.0 V
Characteristics Output current
5 mA
Operating Ambient Temperature
-40 to 85°C
T version: -40 to 85°C
V version: -40 to 125°C (option)
Device Configuration
CMOS high-performance silicon gate
Package
100-pin molded-plastic LQFP
NOTES:
1. I
2
C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
option: All options are on request basis.
Rev.2.10 Aug 25, 2006
REJ03B0058-02100
page 2 of 81
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
Table 1.2 Functions and Specifications for M16C/6N Group (128-pin Version: M16C/6NM)
Item
CPU
Number of fundamental
instructions
Minimum instruction
execution time
Operating mode
Address space
Memory capacity
Ports
Multifunction timers
Specification
Normal-ver.
91 instructions
T/V-ver.
1. Overview
Peripheral
Function
Serial interfaces
A/D converter
D/A converter
DMAC
CRC calculation circuit
CAN module
Watchdog timer
Interrupts
Clock generation circuits
Electrical
Characteristics
Oscillation-stopped detector
Supply voltage
Consumption Mask ROM
current
Flash memory
Mask ROM
Flash memory
Flash Memory Programming and erasure voltage
Version
Programming and erasure endurance
I/O
I/O withstand voltage
Characteristics Output current
Operating Ambient Temperature
Device Configuration
Package
NOTES:
1. I
2
C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
option: All options are on request basis.
41.7 ns (f(BCLK) = 24 MHz,
50.0 ns (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Single-chip, memory expansion, Single-chip mode
and microprocessor modes
1 Mbyte
Refer to
Table 1.3 Product Information
Input/Output: 113 pins, Input: 1 pin
Timer A: 16 bits
✕
5 channels
Timer B: 16 bits
✕
6 channels
Three-phase motor control circuit
3 channels
Clock synchronous, UART, I
2
C-bus
(1)
, IEBus
(2)
4 channels
Clock synchronous
10-bit A/D converter: 1 circuit, 26 channels
8 bits
✕
2 channels
2 channels
CRC-CCITT
2 channels with 2.0B specification
15 bits
✕
1 channel (with prescaler)
Internal: 34 sources, External: 12 sources
Software: 4 sources, Priority levels: 7 levels
4 circuits
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Main clock oscillation stop and re-oscillation detection function
VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
21 mA (f(BCLK) = 24 MHz,
-
PLL operation, no division)
23 mA (f(BCLK) = 24 MHz,
21 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
PLL operation, no division)
3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
0.8 µA (Stop mode, Topr = 25°C)
3.0 ± 0.3 V or 5.0 ± 0.5 V
5.0 ± 0.5 V
100 times
5.0 V
5 mA
-40 to 85°C
T version: -40 to 85°C
V version: -40 to 125°C (option)
CMOS high-performance silicon gate
128-pin molded-plastic LQFP
Rev.2.10 Aug 25, 2006
REJ03B0058-02100
page 3 of 81
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Internal peripheral functions
Timer (16 bits)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
Watchdog timer
(15 bits)
A/D converter
(10 bits
✕
8 channels
Expandable up to 26 channels)
UART or
Clock synchronous serial I/O
(3 channels)
CRC calculation circuit (CCITT)
(Polynomial: X
16
+X
12
+X
5
+1)
System clock generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
(8 bits
✕
4 channels)
(4)
CAN module
(2 channels)
8
Port P8
Port P8_5
7
M16C/60 Series CPU core
R0H
R1H
R0L
R1L
R2
R3
A0
A1
FB
SB
USP
ISP
Memory
ROM
(1)
RAM
(2)
Port P9
DMAC
(2 channels)
8
INTB
Port P10
D/A converter
(8 bits
✕
2 channels)
PC
FLG
Multiplier
8
Port P14
(3)
Port P13
(3)
Port P12
(3)
Port P11
(3)
NOTES:
1: ROM size depends on MCU type.
2: RAM size depends on MCU type.
3: Ports P11 to P14 are only in the 128-pin version.
4: 8 bits
✕
2 channels in the 100-pin version.
2
8
8
8
Figure 1.1 Block Diagram
Rev.2.10 Aug 25, 2006
REJ03B0058-02100
page 4 of 81
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
1.4 Product Information
Table 1.3 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages.
Table 1.3 Product Information
Type No.
M306NKFHGP
M306NMFHGP
M306NKFJGP
M306NMFJGP
M306NKFHTGP
M306NMFHTGP
M306NKFJTGP
M306NMFJTGP
M306NKFHVGP
M306NMFHVGP
M306NKFJVGP
M306NMFJVGP
M306NKME-XXXGP
M306NMME-XXXGP
As of Aug. 2006
ROM Capacity RAM Capacity Package Type
(2)
Remarks
PLQP0100KB-A Flash
Normal-ver.
384 K + 4 Kbytes 31 Kbytes
PLQP0128KB-A memory
PLQP0100KB-A version
(1)
512 K + 4 Kbytes 31 Kbytes
PLQP0128KB-A
PLQP0100KB-A
T-ver.
(D) 384 K + 4 Kbytes 31 Kbytes
PLQP0128KB-A
(D)
PLQP0100KB-A
512 K + 4 Kbytes 31 Kbytes
PLQP0128KB-A
PLQP0100KB-A
V-ver.
(D) 384 K + 4 Kbytes 31 Kbytes
(D)
(D) 512 K + 4 Kbytes 31 Kbytes
(D)
16 Kbytes
192 Kbytes
PLQP0128KB-A
PLQP0100KB-A
PLQP0128KB-A
PLQP0100KB-A Mask
PLQP0128KB-A ROM
Normal-ver.
M306NKMG-XXXGP
20 Kbytes
PLQP0100KB-A version
256 Kbytes
M306NMMG-XXXGP
PLQP0128KB-A
(D): Under development
NOTES:
1. Data flash memory provides an additional 4 Kbytes of ROM capacity (block A).
2. The correspondence between new and old package types is as follows.
PLQP0100KB-A: 100P6Q-A
PLQP0128KB-A: 128P6Q-A
Type No. M30 6N K M G T - XXX GP
Package type:
GP: Package PLQP0100KB-A (100P6Q-A)
PLQP0128KB-A (128P6Q-A)
ROM No.
Omitted on flash memory version
Characteristics
(no) : Normal-ver.
T : T-ver. (Automotive 85°C version)
V : V-ver. (Automotive 125°C version)
ROM capacity:
E : 192 Kbytes
G: 256 Kbytes
H : 384 Kbytes
J : 512 Kbytes
Memory type:
M : Mask ROM version
F : Flash memory version
Shows the number of CAN module, pin count, etc.
6N Group
M16C Family
Figure 1.2 Type Number, Memory Size, and Package
Rev.2.10 Aug 25, 2006
REJ03B0058-02100
page 5 of 81
