M36L0R8060T1
M36L0R8060B1
256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
FEATURES SUMMARY
MULTI-CHIP PACKAGE
– 1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
– 1 die of 64 Mbit (4Mb x16) Pseudo SRAM
■
SUPPLY VOLTAGE
– V
DDF
= V
CCP
= V
DDQF
= 1.7 to 1.95V
– V
PPF
= 9V for fast program (12V tolerant)
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code
M36L0R8060T1: 880Dh
– Bottom Device Code
M36L0R8060B1: 880Eh
■
PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
■
SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
– Asynchronous Page Read mode
– Random Access: 85ns
■
SYNCHRONOUS BURST READ SUSPEND
■
PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
■
MEMORY ORGANIZATION
– Multiple Bank Memory Array: 16 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
■
DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■
SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■
Figure 1. Package
FBGA
TFBGA88 (ZAQ)
8 x 10mm
BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP
F
for Block Lock-Down
– Absolute Write Protection with V
PPF
= V
SS
■
COMMON FLASH INTERFACE (CFI)
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
PSRAM
■
ACCESS TIME: 70ns
■
ASYNCHRONOUS PAGE READ
– Page Size: 16 words
– Subsequent read within page: 20ns
■
LOW POWER FEATURES
– Temperature Compensated Refresh
(TCR)
– Partial Array Refresh (PAR)
– Deep Power-Down (DPD) Mode
■
SYNCHRONOUS BURST READ/WRITE
■
June 2005
1/18
M36L0R8060T1, M36L0R8060B1
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Memory Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSRAM Component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . .
......
......
......
......
......
......
......
......
......
......
.....4
.....4
.....4
.....5
.....6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Inputs (A0-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flash Chip Enable (E
F
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flash Output Enable (G
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flash Write Enable (W
F
).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flash Write Protect (WP
F
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Flash Reset (RP
F
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Chip Enable input (E
P
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Write Enable (W
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Output Enable (G
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Upper Byte Enable (UB
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PSRAM Lower Byte Enable (LB
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PSRAM Configuration Register Enable (CR
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
DDF
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
CCP
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
DDQF
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
PPF
Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
SS
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/18
M36L0R8060T1, M36L0R8060B1
Table 4.
Figure 5.
Figure 6.
Table 5.
Table 6.
Table 7.
Table 8.
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. TFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline . . . . 15
Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/18
M36L0R8060T1, M36L0R8060B1
SUMMARY DESCRIPTION
The M36L0R8060T1 and M36L0R8060B1 com-
bine two memory devices in a Multi-Chip Package:
■
a 256-Mbit, Multiple Bank Flash memory, the
M30L0R8000T0 or M30L0R8000B0,
■
a 64-Mbit PseudoSRAM, the M69KB096AA.
This document should be read in conjunction with
the
M30L0R8000x0
and
M69KB096AA
datasheets.
Recommended operating conditions do not allow
more than one memory to be active at the same
time.
The memory is offered in a Stacked TFBGA88
(8x10mm, 8x10 ball array, 0.8mm pitch) package.
In addition to the standard version, the package is
also available in Lead-free version, in compliance
with JEDEC Std J-STD-020B, the ST ECOPACK
7191395 Specification, and the RoHS (Restriction
of Hazardous Substances) directive. All packages
are compliant with Lead-free soldering processes.
Flash Memory Component
For detailed information on how to use the Flash
memory component, refer to the M30L0R8000(T/
B)0 datasheet which is available from your local
STMicroelectronics distributor.
The memory is supplied with all the bits erased
(set to ‘1’).
PSRAM Component
For detailed information on how to use the PSRAM
component, see the M69KB096AA datasheet that
is available from your local STMicroelectronics
distributor.
Figure 2. Logic Diagram
V
DDQF
V
PPF
V
CCP
16
DQ0-DQ15
E
F
G
F
W
F
RP
F
WP
F
L
K
E
P
G
P
W
P
CR
P
UB
P
LB
P
M36L0R8060T1
M36L0R8060B1
WAIT
V
DDF
24
A0-A23
VSS
AI10533b
4/18
M36L0R8060T1, M36L0R8060B1
Table 1. Signal Names
A0-A23
DQ0-DQ15
L
K
WAIT
V
DDF
V
DDQF
V
PPF
V
SS
V
CCP
NC
DU
Flash Memory Signals
E
F
G
F
W
F
RP
F
WP
F
PSRAM Signals
E
P
G
P
W
P
CR
P
UB
P
LB
P
Chip Enable Input
Output Enable Input
Write Enable Input
Configuration Register Enable Input
Upper Byte Enable Input
Lower Byte Enable Input
Chip Enable input
Output Enable Input
Write Enable input
Reset input
Write Protect input
Address Inputs
Common Data Input/Output
Latch Enable input for Flash memory and PSRAM
Burst Clock for Flash memory and PSRAM
Wait Data in Burst Mode for Flash memory and PSRAM
Flash Memory Power Supply
Flash Power Supply for I/O Buffers
Flash Optional Supply Voltage for Fast Program & Erase
Ground
PSRAM Power Supply
Not Connected Internally
Do Not Use as Internally Connected
5/18
微控制器 MCU
