M36P0R9070E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory
128 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
Feature summary
■
Multi-Chip Package
– 1 die of 512 Mbit (32Mb x 16, Multiple
Bank, Multi-Level, Burst) Flash Memory
– 1
die of 128Mbit (8Mb x16)
PSRAM
Supply voltage
– V
DDF
= V
CCP
= V
DDQ
= 1.7 to 1.95V
– V
PPF
= 9V for fast program
Electronic signature
– Manufacturer Code: 20h
– Device Code: 8819
ECOPACK® package available
FBGA
■
TFBGA107 (ZAC)
■
■
■
Flash memory
■
Block locking
– All Blocks locked at power-up
– Any combination of Blocks can be locked
with zero latency
– WP
F
for Block Lock-Down
– Absolute Write Protection with V
PPF
= V
SS
Synchronous / Asynchronous Read
– Synchronous Burst Read mode:
108MHz, 66MHz
– Asynchronous Page Read mode
– Random Access: 96ns
Programming time
– 4.2µs typical Word program time using
Buffer Enhanced Factory Program
command
Memory organization
– Multiple bank memory array: 64 Mbit banks
– Four Extended Flash Array (EFA) Blocks of
64 Kbits
Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
Security
– 2112-bit user programmable OTP Cells
– 64-bit unique device number
100,000 program/erase cycles per block
Common Flash Interface (CFI)
PSRAM
■
■
Access time: 70ns
User-selectable operating modes
– Asynchronous modes: Random Read, and
Write, Page Read
– Synchronous modes: NOR-Flash, Full
Synchronous (Burst Read and Write)
Asynchronous Page Read
– Page Size: 4, 8 or 16 Words
– Subsequent Read Within Page: 20ns
Burst Read
– Fixed Length (4, 8, 16 or 32 Words) or
Continuous
– Maximum Clock Frequency: 80MHz
Low Power Consumption
– Active Current: < 25mA
– Standby Current: 200µA
– Deep Power-Down Current: 10µA
Low Power Features
– Partial Array Self Refresh (PASR)
– Deep Power-Down (DPD) Mode
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November 2007
Rev 3
1/23
www.numonyx.com
1
Contents
M36P0R9070E0
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Chip Enable input (E
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Output Enable inputs (G
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Write Enable (W
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Write Protect (WP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Reset (RP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Chip Enable input (E
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Write Enable (W
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Output Enable (G
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Upper Byte Enable (UB
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Lower Byte Enable (LB
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Configuration Register Enable (CR
P
) . . . . . . . . . . . . . . . . . . . . . 11
Deep Power-Down input (DPD
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
DDF
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
CCP
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
DDQ
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
PPF
Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
SS
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
4
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/23
M36P0R9070E0
Contents
6
7
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
List of tables
M36P0R9070E0
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4/23
M36P0R9070E0
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA107 8 × 11mm - 9 × 12 active ball array, 0.8mm pitch, package outline. . . . . . . . . 19
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