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Rev. 1.4, Jul. 2011

M378B5773DH0

M391B5773DH0

M378B5273DH0

M391B5273DH0

240pin Unbuffered DIMM

based on 2Gb D-die

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ

-1-

Unbuffered DIMM

datasheet

History

Draft Date

Aug. 2010

Sep. 2010

Nov. 2010

Dec. 2010

Apr. 2011

May. 2011

Jul. 2011

Rev. 1.4

DDR3 SDRAM

Revision History

Revision No.

1.0

1.01

1.1

1.2

1.3

1.31

1.32

1.33

1.34

1.4

- First Release

- Changed note comment on page 31, 39

- Corrected IDD current spec.(IDD7)

- Changed Input/Output capacitance on page 26.

- Changed 1866 speed bin table on page 30.

- Corrected typo.

- Changed timing parameters (Setup/Hold time)

Remark

Editor

S.H.Kim

J.Y.Lee

-2-

Unbuffered DIMM

datasheet

Rev. 1.4

DDR3 SDRAM

Table Of Contents

240pin Unbuffered DIMM based on 2Gb D-die

1. DDR3 Unbuffered DIMM Ordering Information ............................................................................................................. 4

2. Key Features................................................................................................................................................................. 4

3. Address Configuration .................................................................................................................................................. 4

4. x64 DIMM Pin Configurations (Front side/Back side) ................................................................................................... 5

5. x72 DIMM Pin Configurations (Front side/Back side) ................................................................................................... 6

6. Pin Description ............................................................................................................................................................. 7

7. SPD and Thermal Sensor for ECC UDIMMs ................................................................................................................ 7

8. Input/Output Functional Description.............................................................................................................................. 8

8.1 Address Mirroring Feature ....................................................................................................................................... 9

8.1.1. DRAM Pin Wiring Mirroring .............................................................................................................................. 9

9. Function Block Diagram: ............................................................................................................................................... 10

9.1 2GB, 256Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................... 10

9.2 2GB, 256Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ............................................................ 11

9.3 4GB, 512Mx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................... 12

9.4 4GB, 512Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)........................................................... 13

10. Absolute Maximum Ratings ........................................................................................................................................ 14

10.1 Absolute Maximum DC Ratings............................................................................................................................. 14

10.2 DRAM Component Operating Temperature Range .............................................................................................. 14

11. AC & DC Operating Conditions................................................................................................................................... 14

11.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 14

12. AC & DC Input Measurement Levels .......................................................................................................................... 15

12.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 15

12.2 V

REF

Tolerances.................................................................................................................................................... 16

12.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 17

12.3.1. Differential Signals Definition ......................................................................................................................... 17

12.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 17

12.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 18

12.3.4. Differential Input Cross Point Voltage ............................................................................................................ 19

12.4 Slew Rate Definition for Single Ended Input Signals ............................................................................................. 19

12.5 Slew rate definition for Differential Input Signals ................................................................................................... 19

13. AC & DC Output Measurement Levels ....................................................................................................................... 20

13.1 Single Ended AC and DC Output Levels............................................................................................................... 20

13.2 Differential AC and DC Output Levels ................................................................................................................... 20

13.3 Single-ended Output Slew Rate ............................................................................................................................ 20

13.4 Differential Output Slew Rate ................................................................................................................................ 21

14. DIMM IDD specification definition ............................................................................................................................... 22

15. IDD SPEC Table ......................................................................................................................................................... 24

16. Input/Output Capacitance ........................................................................................................................................... 26

17. Electrical Characteristics and AC timing ..................................................................................................................... 27

17.1 Refresh Parameters by Device Density................................................................................................................. 27

17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 27

17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 27

17.3.1. Speed Bin Table Notes .................................................................................................................................. 31

18. Timing Parameters by Speed Grade .......................................................................................................................... 32

18.1 Jitter Notes ............................................................................................................................................................ 38

18.2 Timing Parameter Notes........................................................................................................................................ 39

19. Physical Dimensions................................................................................................................................................... 40

19.1 256Mbx8 based 256Mx64/x72 Module (1 Rank) - M378/91B5773DH0 ................................................................ 40

19.2 256Mbx8 based 512Mx64/x72 Module (2 Ranks) - M378/91B5273DH0 .............................................................. 41

-3-

Unbuffered DIMM

datasheet

Density

2GB

4GB

Organization

256Mx64

256Mx72

512Mx64

512Mx72

Component Composition

256Mx8(K4B2G0846D-HC##)*8

256Mx8(K4B2G0846D-HC##)*9

256Mx8(K4B2G0846D-HC##)*16

256Mx8(K4B2G0846D-HC##)*18

Rev. 1.4

DDR3 SDRAM

Number of

Rank

1. DDR3 Unbuffered DIMM Ordering Information

Part Number

M378B5773DH0-CF8/H9/K0/MA

M391B5773DH0-CF8/H9/K0/MA

M378B5273DH0-CF8/H9/K0/MA

M391B5273DH0-CF8/H9/K0/MA

Height

30mm

NOTE

1. "##" - F8/H9/K0/MA

2. F8 - 1066Mbps 7-7-7/ H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11 / MA - 1866Mbps 13-13-13

- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)

2. Key Features

Speed

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

tRAS(min)

tRC(min)

DDR3-800

6-6-6

2.5

37.5

52.5

DDR3-1066

7-7-7

1.875

13.125

37.5

50.625

DDR3-1333

9-9-9

1.5

13.5

49.5

DDR3-1600

11-11-11

1.25

13.75

48.75

DDR3-1866

13-13-13

1.07

13.91

47.91

Unit

nCK

• JEDEC standard 1.5V ± 0.075V Power Supply

• V

DDQ

= 1.5V ± 0.075V

• 400MHz f

for 800Mb/sec/pin, 533MHz f

for 1066Mb/sec/pin, 667MHz f

for 1333Mb/sec/pin, 800MHz f

for 1600Mb/sec/pin,

933MHz f

for 1866Mb/sec/pin

• 8 independent internal bank

• Programmable CAS Latency: 6,7,8,9,10,11,13

• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866)

• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

CASE

85°C, 3.9us at 85°C < T

CASE

≤

95°C

• Asynchronous Reset

3. Address Configuration

Organization

256Mx8(2Gb) based Module

Row Address

A0-A14

Column Address

A0-A9

Bank Address

BA0-BA2

Auto Precharge

A10/AP

-4-

Unbuffered DIMM

datasheet

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

Rev. 1.4

DDR3 SDRAM

4. x64 DIMM Pin Configurations (Front side/Back side)

Front

REFDQ

DQ0

DQ1

DQS0

DQ2

DQ3

DQ8

DQ9

DQS1

DQ10

DQ11

DQ16

DQ17

DQS2

DQ18

DQ19

DQ24

DQ25

DQS3

DQ26

DQ27

Back

DQ4

DQ5

DM0

DQ6

DQ7

DQ12

DQ13

DM1

DQ14

DQ15

DQ20

DQ21

DM2

DQ22

DQ23

DQ28

DQ29

DM3

DQ30

DQ31

Front

KEY

162

163

164

165

166

167

168

Back

NC (TEST)

Reset

Front

DQ33

DQS4

DQ34

DQ35

DQ40

DQ41

DQS5

DQ42

DQ43

DQ48

DQ49

DQS6

DQ50

DQ51

DQ56

DQ57

DQS7

DQ58

DQ59

SA0

SCL

SA2

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Back

DM4

DQ38

DQ39

DQ44

DQ45

DM5

DQ46

DQ47

DQ52

DQ53

DM6

DQ54

DQ55

DQ60

DQ61

DM7

DQ62

DQ63

DDSPD

SA1

SDA

CKE0

BA2

A11

CK1,NC

REF

A10/AP

BA0

CAS

S1, NC

ODT1, NC

DQ32

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

CKE1,NC

A14

A12/BC

CK0

BA1

RAS

ODT0

A13

DQ36

DQ37

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

NOTE

NC = No Connect; NU = Not Used; RFU = Reserved Future Use

1. S1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs

2. CK1,NC and CK1,NC : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated

3. TEST (pin 167) used by memory bus analysis tools (unused on memory DIMMs)

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

-5-