3803 Group (Spec.L)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0212-0101
Rev.1.01
Jan 25, 2008
• Power source voltage (Flash memory version)
[In high-speed mode]
At 16.8 MHz oscillation frequency .................... 4.5 to 5.5 V
At 12.5 MHz oscillation frequency .................... 4.0 to 5.5 V
At 8.4 MHz oscillation frequency ...................... 2.7 to 5.5 V
[In middle-speed mode]
At 16.8 MHz oscillation frequency .................... 4.5 to 5.5 V
At 12.5 MHz oscillation frequency .................... 2.7 to 5.5 V
[In low-speed mode]
At 32 kHz oscillation frequency......................... 2.7 to 5.5 V
• Power dissipation (Mask ROM version)
In high-speed mode ........................................... 40 mW (typ.)
(at 16.8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............................................ 45
µW
(typ.)
(at 32 kHz oscillation frequency, at 3 V power source voltage)
• Power dissipation (Flash memory version)
In high-speed mode ........................................ 27.5 mW (typ.)
(at 16.8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ........................................ 1200
µW
(typ.)
(at 32 kHz oscillation frequency, at 3 V power source voltage)
• Operating temperature range .............................
−20
to 85
°C
• Packages
SP...............PRDP0064BA-A (64P4B) (64-pin 750 mil SDIP)
HP ......PLQP0064KB-A (64P6Q-A) (64-pin 10 × 10 mm LQFP)
KP ......PLQP0064GA-A (64P6U-A) (64-pin 14 × 14 mm LQFP)
WG ........PTLG0064JA-A (64F0G) (64-pin 6 × 6 mm FLGA)
<Flash memory mode>
• Power source voltage ................................ V
CC
= 2.7 to 5.5 V
• Program/Erase voltage ............................. V
CC
= 2.7 to 5.5 V
• Programming method ............... Programming in unit of byte
• Erasing method ................................................. Block erasing
• Program/Erase control by software command
• Number of times for programming/erasing ...................... 100
<Notes>
The flash memory version cannot be used for application
embedded in the MCU card.
DESCRIPTION
The 3803 group (Spec.L) is the 8-bit microcomputer based on the
740 family core technology.
The 3803 group (Spec.L) is designed for household products,
office automation equipment, and controlling systems that
require analog signal processing, including the A/D converter
and D/A converters.
FEATURES
• Basic machine-language instructions ................................. 71
• Minimum instruction execution time .......................... 0.24
µs
(at 16.8 MHz oscillation frequency)
• Memory size
Mask ROM/Flash memory .................................... 60 K bytes
RAM ...................................................................... 2048 bytes
• Programmable input/output ports ....................................... 56
• Software pull-up resistors ............................................ Built-in
• Interrupts
21 sources, 16 vectors...............................................................
(external 8, internal 12, software 1)
• Timers ...................................................................... 16-bit × 1
8-bit × 4
(with 8-bit prescaler)
• Serial interface ......... 8-bit × 2 (UART or Clock-synchronized)
8-bit × 1 (Clock-synchronized)
• PWM ....................................... 8-bit × 1 (with 8-bit prescaler)
• A/D converter ........................................ 10-bit × 16 channels
(8-bit reading enabled)
• D/A converter ............................................ 8-bit × 2 channels
• Watchdog timer ....................................................... 16-bit × 1
• LED direct drive port..............................................................8
• Clock generating circuit ............................. Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage (Mask ROM version)
[In high-speed mode]
At 16.8 MHz oscillation frequency ....................4.5 to 5.5 V
At 12.5 MHz oscillation frequency ....................4.0 to 5.5 V
At 8.4 MHz oscillation frequency ......................2.7 to 5.5 V
At 4.2 MHz oscillation frequency ......................2.2 to 5.5 V
At 2.1 MHz oscillation frequency ......................2.0 to 5.5 V
[In middle-speed mode]
At 16.8 MHz oscillation frequency ....................4.5 to 5.5 V
At 12.5 MHz oscillation frequency ....................2.7 to 5.5 V
At 8.4 MHz oscillation frequency ......................2.2 to 5.5 V
At 6.3 MHz oscillation frequency ......................1.8 to 5.5 V
[In low-speed mode]
At 32 kHz oscillation frequency.........................1.8 to 5.5 V
Rev.1.01 Jan 25, 2008
REJ03B0212-0101
Page 1 of 117
3803 Group (Spec.L)
P1
0
/INT
41
P1
1
/INT
01
P0
2
/AN
10
P0
3
/AN
11
P0
4
/AN
12
P0
5
/AN
13
P0
6
/AN
14
P0
7
/AN
15
P0
0
/AN
8
P0
1
/AN
9
P1
2
P1
3
P1
4
P1
5
P1
6
34
48
47
46
45
44
43
42
41
40
39
38
37
36
35
P3
7
/S
RDY3
P3
6
/S
CLK3
P3
5
/T
X
D
3
P3
4
/R
X
D
3
P3
3
P3
2
P3
1
/DA
2
P3
0
/DA
1
V
CC
V
REF
AV
SS
P6
7
/AN
7
P6
6
/AN
6
P6
5
/AN
5
P6
4
/AN
4
P6
3
/AN
3
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
33
P1
7
32
31
30
29
28
27
26
P2
0
(LED
0
)
P2
1
(LED
1
)
P2
2
(LED
2
)
P2
3
(LED
3
)
P2
4
(LED
4
)
P2
5
(LED
5
)
P2
6
(LED
6
)
P2
7
(LED
7
)
V
SS
X
OUT
X
IN
P4
0
/INT
40
/X
COUT
P4
1
/INT
00
/X
CIN
RESET
CNV
SS
P4
2
/INT
1
M38039MFL-XXXHP/KP
M38039FFLHP/KP
25
24
23
22
21
20
19
18
17
P5
5
/CNTR
1
P5
4
/CNTR
0
P5
1
/S
OUT2
P6
2
/AN
2
P6
1
/AN
1
P6
0
/AN
0
P5
7
/INT
3
P4
7
/S
RDY1
/CNTR
2
P4
5
/T
X
D
1
P4
4
/R
X
D
1
P5
2
/S
CLK2
Package code : PLQP0064KB-A (64P6Q-A)/PLQP0064GA-A (64P6U-A)
Fig 1.
Pin configuration (Top view) PLQP0064KB-A (64P6Q-A)/PLQP0064GA-A (64P6U-A)
V
CC
V
REF
AV
SS
P6
7
/AN
7
P6
6
/AN
6
P6
5
/AN
5
P6
4
/AN
4
P6
3
/AN
3
P6
2
/AN
2
P6
1
/AN
1
P6
0
/AN
0
P5
7
/INT
3
P5
6
/PWM
P5
5
/CNTR
1
P5
4
/CNTR
0
P5
3
/S
RDY2
P5
2
/S
CLK2
P5
1
/S
OUT2
P5
0
/S
IN2
P4
7
/S
RDY1
/
CNTR
2
P4
6
/S
CLK1
P4
5
/T
X
D
1
P4
4
/R
X
D
1
P4
3
/INT
2
P4
2
/INT
1
CNV
SS
RESET
P4
1
/INT
00
/X
CIN
P4
0
/INT
40
/X
COUT
X
IN
X
OUT
V
SS
P5
3
/S
RDY2
P4
6
/S
CLK1
P5
6
/PWM
P4
3
/INT
2
P5
0
/S
IN2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P3
0
/DA
1
P3
1
/DA
2
P3
2
P3
3
P3
4
/R
X
D
3
P3
5
/T
X
D
3
P3
6
/
S
CLK3
P3
7
/
S
RDY3
P0
0
/AN
8
P0
1
/AN
9
P0
2
/AN
10
P0
3
/AN
11
P0
4
/AN
12
P0
5
/AN
13
P0
6
/AN
14
P0
7
/AN
15
P1
0
/
INT
41
P1
1
/
INT
01
P1
2
P1
3
P1
4
P1
5
P1
6
P1
7
P2
0
(LED
0
)
P2
1
(LED
1
)
P2
2
(LED
2
)
P2
3
(LED
3
)
P2
4
(LED
4
)
P2
5
(LED
5
)
P2
6
(LED
6
)
P2
7
(LED
7
)
Package code : PRDP0064BA-A (64P4B)
Fig 2.
Pin configuration (Top view) (PRDP0064BA-A (64P4B))
M38039MFL-XXXSP
M38039FFLSP
Rev.1.01 Jan 25, 2008
REJ03B0212-0101
Page 2 of 117
3803 Group (Spec.L)
PIN CONFIGURATION (TOP VIEW)
A
B
C
D
E
F
G
H
8
50
P3
6
/S
CLK3
46
P0
2
/AN
10
44
P0
4
/AN
12
41
P0
7
/AN
15
40
P1
0
/INT
41
32
P2
0
(LED
0
)
31
P2
1
(LED
1
)
30
P2
2
(LED
2
)
8
7
51
P3
5
/T
X
D
3
47
P0
1
/AN
9
45
P0
3
/AN
11
42
P0
6
/AN
14
39
P1
1
/INT
01
27
P2
5
(LED
5
)
29
P2
3
(LED
3
)
28
P2
4
(LED
4
)
7
6
53
P3
3
52
P3
4
/R
X
D
3
48
P0
0
/AN
8
43
P0
5
/AN
13
38
P1
2
37
P1
3
26
P2
6
(LED
6
)
25
P2
7
(LED
7
)
6
5
56
P3
0
/DA
1
55
P3
1
/DA
2
54
P3
2
49
P3
7
/S
RDY3
33
P1
7
36
P1
4
35
P1
5
34
P1
6
5
4
1
P6
2
/AN
2
64
P6
3
/AN
3
58
V
REF
59
AV
SS
57
V
CC
24
V
SS
22
X
IN
23
X
OUT
4
3
60
P6
7
/AN
7
61
P6
6
/AN
6
4
P5
7
/INT
3
7
P5
4
/CNTR
0
12
P4
7
/S
RDY1
/CNTR
2
14
P4
5
/T
X
D
1
21
P4
0
/INT
40
/X
COUT
20
P4
1
/INT
00
/X
CIN
3
2
62
P6
5
/AN
5
63
P6
4
/AN
4
5
P5
6
/PWM
8
P5
3
/S
RDY2
10
P5
1
/S
OUT2
13
P4
6
/S
CLK1
17
P4
2
/INT
1
19
RESET
2
1
2
P6
1
/AN
1
3
P6
0
/AN
0
6
P5
5
/CNTR
1
9
P5
2
/S
CLK2
11
P5
0
/S
IN2
15
P4
4
/R
X
D
1
16
P4
3
/INT
2
18
CNV
SS
1
A
B
C
D
E
F
G
H
Package code : PTLG0064JA-A (64F0G)
Note : The numbers in circles corresponds with the number on the packages HP/KP.
M38039MFL
-XXXWG
M38039
FFLWG
Package (TOP VIEW)
Fig 3.
Pin configuration (Top view) (PTLG0064JA-A (64F0G))
Rev.1.01 Jan 25, 2008
REJ03B0212-0101
Page 3 of 117
3803 Group (Spec.L)
Table 1
Performance overview
Parameter
Function
71
0.24
µs
(Oscillation frequency 16.8 MHz)
Oscillation frequency 16.8 MHz(Maximum)
ROM
RAM
Flash memory version
ROM
RAM
60 Kbytes
2048 bytes
60 Kbytes
2048 bytes
56 pins
Built-in
21 sources, 16 vectors (8 external, 12 internal, 1 software)
8-bit
×
4 (with 8-bit prescaler), 16-bit
×
1
8-bit
×
2 (UART or Clock-synchronized)
8-bit
×
1 (Clock-synchronized)
8-bit
×
1 (with 8-bit prescaler)
10-bit
×
16 channels (8-bit reading enabled)
8-bit
×
2 channels
16-bit
×
1
8 (average current: 15 mA, peak current: 30 mA, total current: 90 mA)
Built-in 2 circuits
(connect to external ceramic rasonator or quartz-crystal oscillator)
At 16.8 MHz
At 12.5 MHz
At 8.4 MHz
At 4.2 MHz
At 2.1 MHz
In middle-
speed mode
At 16.8 MHz
At 12.5 MHz
At 8.4 MHz
At 6.3 MHz
In low-speed
mode
At 32 MHz
Mask ROM version
Flash memory version
Mask ROM version
Flash memory version
Mask ROM version
Flash memory version
Mask ROM version
Mask ROM version
Mask ROM version
Flash memory version
Mask ROM version
Flash memory version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
4.5 to 5.5 V
4.0 to 5.5 V
2.7 to 5.5 V
2.2 to 5.5 V
2.0 to 5.5 V
4.5 to 5.5 V
2.7 to 5.5 V
2.2 to 5.5 V
1.8 to 5.5 V
1.8 to 5.5 V
40 mW
45
µW
V
CC
10 mA
-20 to 85
°C
CMOS sillicon gate
64-pin plastic molded SDIP/LQFP/FLGA
Number of basic instructions
Minimum instruction execution time
Oscillation frequency
Memory
sizes
Mask ROM version
I/O port
Interrupt
Timer
P0-P6
Software pull-up resistors
Serial interface
PWM
A/D converter
D/A converter
Watchdog timer
LED direct drive port
Clock generating circuits
Power
source
voltage
In high-speed
mode
Flash memory version 2.7 to 5.5 V
Flash memory version 27.5 mW
Power
dissipation
In high-speed mode
In low-speed mode
Flash memory version 1200
µW
Input/Output Input/Output withstand voltage
characteris- Output current
tics
Operating temperature range
Device structure
Package
Rev.1.01 Jan 25, 2008
REJ03B0212-0101
Page 4 of 117
3803 Group (Spec.L)
Fig 4.
Reset input
V
SS
V
CC
1
26
27
32
FUNCTIONAL BLOCK DIAGRAM (Package: PRDP0064BA-A (64P4B))
RESET
CNV
SS
Main
clock
input
X
IN
Main
clock
output
X
OUT
Sub-clock Sub-clock
input
output
X
CIN
X
COUT
30
31
28
29
Rev.1.01 Jan 25, 2008
REJ03B0212-0101
Data bus
C P U
Functional block diagram
ROM
X
Prescaler 12 (8)
Clock generating circuit
RAM
A
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Timer Y (8)
Prescaler Y (8)
CNTR
1
Y
Prescaler X (8)
Page 5 of 117
S
CNTR
0
PC
H
PS
CNTR
2
PC
L
Timer Z (16)
0
A/D
converter
(10)
SI/O2 (8)
SI/O1 (8)
PWM (8)
D/A
converter
2 (8)
D/A
converter
1 (8)
SI/O3 (8)
INT
3
INT
01
INT
41
P6 (8)
P5 (8)
P4 (8)
INT
00
INT
1
INT
2
INT
40
P3 (8)
P2 (8)
P1 (8)
P0 (8)
2
3
4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19
20 21 22 23 24 25 28 29
57 58 59 60 61 62 63 64
33 34 35 36 37 38 39 40
41 42 43 44 45 46 47 48
49 50 51 52 53 54 55 56
V
REF
AV
SS
I/O port P6
I/O port P5
I/O port P4
I/O port P3
I/O port P2
(LED drive)
I/O port P1
I/O port P0
