38D2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 38D2 Group is the 8-bit microcomputer based on the 740
Family core technology.
The 38D2 Group is pin-compatible with the 38C2 Group.
The 38D2 Group has an LCD drive control circuit, an A/D
converter, a serial interface, and a ROM correction function and
on-chip oscillator as additional functions.
The QzROM version and the flash memory version are available.
The flash memory version does not have a selection function for
the oscillation start mode. Only the on-chip oscillator starts
oscillating.
The various microcomputers include variations of memory size,
and packaging. For details, refer to the section on part
numbering.
FEATURES
• Basic machine-language instructions ................................. 71
• The minimum instruction execution time ................... 0.32
μs
(at 12.5 MHz oscillation frequency)
• Memory size (QzROM version)
ROM ........................................................ 16 K to 60 K bytes
RAM ........................................................... 640 to 2048 bytes
• Memory size (Flash memory version)
ROM ...................................................................... 60 K bytes
RAM ...................................................................... 2048 bytes
• Programmable input/output ports .. 51 (common to SEG: 24)
• Interrupts ............................................. 18 sources, 16 vectors
• Timers ..................................................... 8-bit × 4, 16-bit × 2
• Serial interface ....... 8-bit × 2 (UART or Clock-synchronized)
• PWM .......... 10-bit × 2, 16-bit × 1 (common to IGBT output)
• A/D converter .......................................... 10-bit × 8 channels
(A/D converter can be operated in low-speed mode.)
• Watchdog timer ......................................................... 8-bit × 1
• ROM correction function ....................... 32 bytes × 2 vectors
• LED direct drive port ............................................................ 8
(average current: 15 mA, peak current: 30 mA, total current: 90 mA)
• LCD drive control circuit
Bias ............................................................................ 1/2, 1/3
Duty .............................................................................. 2, 3, 4
Common output .................................................................... 4
Segment output ................................................................... 24
• Main clock generating circuit ............................................... 1
(connect to external ceramic resonator or on-chip oscillator)
• Sub-clock generating circuit ..................................................1
(connect to external quartz-crystal oscillator)
REJ03B0177-0302
Rev.3.02
Apr 10, 2008
• Power source voltage (QzROM version)
[In frequency/2 mode]
f(X
IN
)
≤
12.5 MHz.............................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 4.0 to 5.5 V
f(X
IN
)
≤
4 MHz................................................... 2.0 to 5.5 V
f(X
IN
)
≤
2 MHz................................................... 1.8 to 5.5 V
[In frequency/4 mode]
f(X
IN
)
≤
16 MHz................................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 2.0 to 5.5 V
f(X
IN
)
≤
4 MHz................................................... 1.8 to 5.5 V
[In frequency/8 mode]
f(X
IN
)
≤
16 MHz................................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 2.0 to 5.5 V
f(X
IN
)
≤
4 MHz................................................... 1.8 to 5.5 V
[In low-speed mode].............................................. 1.8 to 5.5 V
Note. 12.5 MHz < f(X
IN
)
≤
16 MHz is not available in the fre-
• Power source voltage (Flash memory version)
[In frequency/2 mode]
f(X
IN
)
≤
12.5 MHz.............................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 4.0 to 5.5 V
f(X
IN
)
≤
4 MHz................................................... 2.7 to 5.5 V
[In frequency/4 mode]
f(X
IN
)
≤
16 MHz................................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 2.7 to 5.5 V
[In frequency/8 mode]
f(X
IN
)
≤
16 MHz................................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 2.7 to 5.5 V
[In low-speed mode].............................................. 2.7 to 5.5 V
Note. 12.5 MHz < f(X
IN
)
≤
16 MHz is not available in the fre-
• Power dissipation (QzROM version)
• In frequency/2 mode ..................................... Typ. 32 mW
(V
CC
= 5 V, f(X
IN
) = 12.5 MHz, Ta = 25°C)
• In low-speed mode ........................................ Typ. 18
μW
(V
CC
= 2.5 V, f(X
IN
) = stop, f(X
CIN
) = 32 kHz, Ta = 25°C)
• Power dissipation (Flash memory version)
• In frequency/2 mode ..................................... Typ. 20 mW
(V
CC
= 5 V, f(X
IN
) = 12.5 MHz, Ta = 25°C)
• In low-speed mode ...................................... Typ. 1.1 mW
(V
CC
= 2.7 V, f(X
IN
) = stop, f(X
CIN
) = 32 kHz, Ta = 25°C)
• Operating temperature range ...............................
−20
to 85°C
Flash Memory Mode
• Program/Erase voltage ............................. V
CC
= 2.7 to 5.5 V
• Program method ....................... Programming in unit of byte
• Erase method .................................................... Block erasing
• Program/Erase control by software command
quency/2 mode.
quency/2 mode.
APPLICATION
Household products, Consumer electronics, etc.
Rev.3.02 Apr 10, 2008
REJ03B0177-0302
Page 1 of 131
38D2 Group
PIN CONFIGURATION
(TOP VIEW)
P0
4
/SEG
4
P0
5
/SEG
5
P0
6
/SEG
6
P0
7
/SEG
7
P1
0
/SEG
8
P1
1
/SEG
9
P1
2
/SEG
10
P1
3
/SEG
11
P1
4
/SEG
12
P1
5
/SEG
13
P1
6
/SEG
14
P1
7
/SEG
15
P2
0
/SEG
16
P2
1
/SEG
17
P2
2
/SEG
18
P2
3
/SEG
19
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P0
3
/SEG
3
/(KW
7
)
P0
2
/SEG
2
/(KW
6
)
P0
1
/SEG
1
/(KW
5
)
P0
0
/SEG
0
/(KW
4
)
P5
7
/S
RDY1
/(KW
3
)
P5
6
/S
CLK1
/(KW
2
)
P5
5
/T
X
D
1
/(KW
1
)
P5
4
/R
X
D
1
/(KW
0
)
P5
3
/T
4OUT
/PWM
1
P5
2
/T
3OUT
/PWM
0
P5
1
/INT
1
P5
0
/INT
0
AV
SS
VREF
P4
7
/RTP
1
/AN
7
P4
6
/RTP
0
/AN
6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
M38D2XGXFP/HP
M38D29FFFP/HP
P2
4
/SEG
20
P2
5
/SEG
21
P2
6
/SEG
22
/V
L1
P2
7
/SEG
23
/V
L2
V
L3
COM
0
COM
1
COM
2
COM
3
P3
0
/S
RDY2
/(LED
0
)
P3
1
/S
CLK2
/(LED
1
)
P3
2
/T
X
D
2
/(LED
2
)
P3
3
/R
X
D
2
/(LED
3
)
P3
4
/INT
2
/(LED
4
)
P3
5
/T
XOUT1
/(LED
5
)
P3
6
/T
2OUT
/CKOUT/(LED
6
)
RESET
P6
2
/X
COUT
P6
1
/X
CIN
V
SS
X
IN
X
OUT
V
CC
P6
0
/CNTR
1
P3
7
/CNTR
0
/T
XOUT2
/(LED
7
)
P4
5
/AN
5
P4
4
/AN
4
P4
3
/AN
3
P4
2
/ADKEY/AN
2
P4
1
/O
OUT1
/AN
1
P4
0
/O
OUT0
/AN
0
OSCSEL
(Note 1)
Note 1: CNV
SS
in flash
memory version
Package type : PLQP0064GA-A(64P6U-A)/PLQP0064KB-A(64P6Q-A)
Fig. 1 Pin configuration (LQFP Package)
Rev.3.02 Apr 10, 2008
REJ03B0177-0302
Page 2 of 131
38D2 Group
Table 1
Performance overview
Parameter
Function
71
0.32
μs
(Minimum instruction, Oscillation frequency 12.5 MHz)
16 MHz (Maximum)
(1)
ROM
RAM
16 K to 60 K bytes
640 to 2048 bytes
60 K bytes
2048 bytes
8-bit
×
6, 3-bit
×
1 (24 pins sharing SEG)
18 sources, 16 vectors (includes key input interrupt)
8-bit
×
4, 16-bit
×
2
8-bit
×
2 (UART or Clock-synchronized)
10-bit
×
2, 16-bit
×
1 (common to IGBT output)
10-bit
×
8 (operated in low-speed mode)
8-bit
×
1
32 bytes
×
2 vectors
8 (average current: 15 mA, peak current: 30 mA, total current: 90 mA)
Bias
Duty
Common output
Segment output
1/2, 1/3
2, 3, 4
4
24
Built-in (connect to external ceramic resonator or on-chip oscillator)
Built-in (connect to external quartz-crystal oscillator)
f(X
IN
)
≤
12.5 MHz 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
4 MHz
f(X
IN
)
≤
2 MHz
In frequency/4 mode
f(X
IN
)
≤
16 MHz
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
4 MHz
In frequency/8 mode
f(X
IN
)
≤
16 MHz
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
4 MHz
In low-speed mode
4.0 to 5.5 V
2.0 to 5.5 V
1.8 to 5.5 V
4.5 to 5.5 V
2.0 to 5.5 V
1.8 to 5.5 V
4.5 to 5.5 V
2.0 to 5.5 V
1.8 to 5.5 V
1.8 to 5.5 V
f(X
IN
)
≤
12.5 MHz 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
4 MHz
In frequency/4 mode
In frequency/8 mode
In low-speed mode
f(X
IN
)
≤
16 MHz
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
16 MHz
f(X
IN
)
≤
8 MHz
4.0 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
2.7 to 5.5 V
2.7 to 5.5 V
Std. 32 mW (Vcc = 5 V, f(X
IN
) = 12.5 MHz, Ta = 25°C)
Std. 18
μW
(Vcc = 2.5 V, f(X
IN
) = stop, f(X
CIN
) = 32 kHz, Ta = 25°C)
Std. 20 mW (Vcc = 5 V, f(X
IN
) = 12.5 MHz, Ta = 25°C)
Std. 1.1 mW (Vcc = 2.7 V, f(X
IN
) = stop, f(X
CIN
) = 32 kHz, Ta = 25°C)
V
CC
10 mA
-20 to 85°C
CMOS silicon gate
64-pin plastic molded LQFP
Number of basic instructions
Instruction execution time
Oscillation frequency
Memory sizes
(QzROM version)
ROM
Memory sizes
(Flash memory version) RAM
I/O port
Interrupt
Timer
Serial Interface
PWM
A/D converter
Watchdog timer
ROM correction function
LED direct drive port
LCD drive control
circuit
P0-P5, P6
0
-P6
2
Main clock generating circuits
Sub-clock generating circuits
Power source voltage
(QzROM version)
In frequency/2 mode
(1)
Power source voltage In frequency/2 mode
(Flash memory version)
(1)
Power dissipation
(QzROM version)
In frequency/2 mode
In low-speed mode
In frequency/2 mode
Power dissipation
(Flash memory version) In low-speed mode
Input/Output
characteristics
Device structure
Package
Input/Output withstand voltage
Output current
Operating temperature range
NOTE:
1. 12.5 MHz < f(X
IN
)
≤
16 MHz is not available in the frequency/2 mode.
Rev.3.02 Apr 10, 2008
REJ03B0177-0302
Page 3 of 131
38D2 Group
FUNCTIONAL BLOCK DIAGRAM
8
8
8
---------------------------------------------------------------------------------------------------------------------------------------------
Rev.3.02 Apr 10, 2008
REJ03B0177-0302
Port P1 (8)
Port P2 (8)
Port P3 (8)
Timer
On-chip
oscillator
Fig. 2 Functional block diagram
System clock
φ
generation
Timer X (16 bits)
PWM (16 bits)
IGBT output
Timer Y (16 bits)
Timer 1 (8 bits)
Timer 2 (8 bits)
Timer 3 (8 bits)
PWM0 (10 bits)
Timer 4 (8 bits)
PWM1 (10 bits)
---------------------------------------------------------------------------------------------------------------------------------------------
8
Port P0 (8)
Internal peripheral function
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
Page 4 of 131
Serial I/O
X
IN
–X
OUT
(Main clock)
X
CIN
–X
COUT
(Sub-clock)
A/D converter
10-bits
×
8-channels
Serial I/O1
(UART or Clock synchronous)
Serial I/O2
(UART or Clock synchronous)
Memory
ROM
CPU core
ROM correction
LCD drive control circuit
RAM for LCD display
(12 bytes)
4 COM
×
24 SEG
RAM
Watchdog timer
Port P4 (8)
8
3
Port P5 (8)
Port P6 (3)
8
38D2 Group
PIN DESCRIPTION
Table 2
Pin description (1)
Pin
V
CC
, V
SS
RESET
X
IN
X
OUT
Name
Power source
Reset input
Clock input
Clock output
Function
• Apply 1.8 to 5.5 V to V
CC
, and 0 V to V
SS
.
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the X
IN
and X
OUT
pins to
set the oscillation frequency. When an external clock is used, connect the clock source to
X
IN
, and leave X
OUT
pin open.
• Feedback resistor is built in between X
IN
pin and X
OUT
pin.
• Input 0
≤
V
L1
≤
V
L2
≤
V
L3
voltage.
• Input 0
−
V
L3
voltage to LCD.
• LCD common output pins.
• COM
2
and COM
3
are not used at 1/2 duty ratio.
• COM
3
is not used at 1/3 duty ratio.
•
•
•
•
• LCD segment
8-bit I/O port.
output pins
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in a bit unit.
• Key input interrupt
input pins
Function except a port function
V
L3
COM
0
−
COM
3
P0
0
/SEG
0
/(KW
4
)−
P0
3
/SEG
3
/(KW
7
)
P0
4
/SEG
4
−
P0
7
/SEG
7
LCD power
source
Common output
I/O port P0
P1
0
/SEG
8
−
P1
7
/SEG
15
I/O port P1
•
•
•
•
P2
0
/SEG
16
−
P2
5
/SEG
21
P2
6
/SEG
22
/V
L1
P2
7
/SEG
23
/V
L2
I/O port P2
•
•
•
•
• LCD power source
pins
P3
0
/S
RDY2
/(LED
0
)
P3
1
/S
CLK2
/(LED
1
)
P3
2
/TxD
2
/(LED
2
)
P3
3
/RxD
2
/(LED
3
)
P3
4
/INT
2
/(LED
4
)
P3
5
/T
XOUT1
/(LED
5
)
P3
6
/T
2OUT
/CKOUT/
(LED
6
)
P3
7
/CNTR
0
/T
XOUT2
/
(LED
7
)
P4
0
/O
OUT0
/AN
0
P4
1
/O
OUT1
/AN
1
P4
2
/AN
2
/ADKEY
P4
3
/AN
3
−P4
5
/AN
5
P4
6
/RTP
0
/AN
6
P4
7
/RTP
1
/AN
7
P5
0
/INT
0
P5
1
/INT
1
P5
2
/T
3OUT
/PWM
0
P5
3
/T
4OUT
/PWM
1
P5
4
/RxD
1
/(KW
0
)
P5
5
/TxD
1
/(KW
1
)
P5
6
/S
CLK1
/(KW
2
)
P5
7
/S
RDY1
/(KW
3
)
I/O port P3
•
•
•
•
• Serial I/O2 function pins
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output. • External interrupt pin
• Pull-up control is enabled in 4-bit unit.
• Timer X, Timer 2 output pins
• Timer X function pin
I/O port P4
•
•
•
•
• A/D convertor
8-bit I/O port.
input pins
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in 4-bit unit.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be
individually programmed as either input or output.
• Pull-up control is enabled in 4-bit unit
• External input pins
• Timer 3, Timer 4 output pins
• PWM output pins
• Serial I/O1 function pins
• Key input interrupt input pins
• Oscillation
external output
pins
• ADKEY
• Real time port
function pins
I/O port P5
•
•
•
•
Rev.3.02 Apr 10, 2008
REJ03B0177-0302
Page 5 of 131
