38D5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 38D5 Group is the 8-bit microcomputer based on the 740
Family core technology.
The 38D5 Group is pin-compatible with the 38C5 Group.
The 38D5 Group has an LCD drive control circuit, an A/D
converter, a serial interface, and a ROM correction function as
additional functions.
The QzROM version and the flash memory version are available.
The flash memory version does not have a selection function for
the oscillation start mode. Only the on-chip oscillator starts
oscillating.
The various microcomputers include variations of memory size,
and packaging. For details, refer to the section on part
numbering.
FEATURES
• Basic machine-language instructions ................................. 71
• The minimum instruction execution time ................... 0.32
µs
(at 12.5 MHz oscillation frequency)
• Memory size (QzROM version)
ROM ........................................................ 32 K to 60 K bytes
RAM ......................................................... 1536 to 2048 bytes
• Memory size (Flash memory version)
ROM ...................................................................... 60 K bytes
RAM ...................................................................... 2048 bytes
• Programmable input/output ports .. 59 (common to SEG: 36)
• Interrupts ............................................. 17 sources, 16 vectors
(Key input interrupt included)
• Timers ..................................................... 8-bit × 4, 16-bit × 2
• Serial interface
Serial I/O1 ...............8-bit × 1 (UART or Clock-synchronized)
Serial I/O2 .............................. 8-bit × 1 (Clock-synchronized)
• PWM .......... 10-bit × 2, 16-bit × 1 (common to IGBT output)
• A/D converter .......................................... 10-bit × 8 channels
(A/D converter can be operated in low-speed mode.)
• Watchdog timer ......................................................... 8-bit × 1
• ROM correction function ....................... 32 bytes × 2 vectors
• LED direct drive port ............................................................ 6
(average current: 15 mA, peak current: 30 mA, total current: 90 mA)
• LCD drive control circuit
Bias ............................................................................ 1/2, 1/3
Duty ............................................................... Static, 2, 3, 4, 8
Common output ................................................................. 4/8
Segment output .............................................................. 32/36
• Main clock generating circuit ............................................... 1
(connect to external ceramic resonator or on-chip oscillator)
• Sub-clock generating circuit ..................................................1
(connect to external quartz-crystal oscillator)
REJ03B0158-0301
Rev.3.01
Aug 08, 2007
• Power source voltage (QzROM version)
[In frequency/2 mode]
f(X
IN
)
≤
12.5 MHz.............................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 4.0 to 5.5 V
f(X
IN
)
≤
4 MHz................................................... 2.0 to 5.5 V
f(X
IN
)
≤
2 MHz................................................... 1.8 to 5.5 V
[In frequency/4 mode]
f(X
IN
)
≤
16 MHz................................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 2.0 to 5.5 V
f(X
IN
)
≤
4 MHz................................................... 1.8 to 5.5 V
[In frequency/8 mode]
f(X
IN
)
≤
16 MHz................................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 2.0 to 5.5 V
f(X
IN
)
≤
4 MHz................................................... 1.8 to 5.5 V
[In low-speed mode].............................................. 1.8 to 5.5 V
Note. 12.5 MHz < f(X
IN
)
≤
16 MHz is not available in the fre-
• Power source voltage (Flash memory version)
[In frequency/2 mode]
f(X
IN
)
≤
12.5 MHz.............................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 4.0 to 5.5 V
f(X
IN
)
≤
4 MHz................................................... 2.7 to 5.5 V
[In frequency/4 mode]
f(X
IN
)
≤
16 MHz................................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 2.7 to 5.5 V
[In frequency/8 mode]
f(X
IN
)
≤
16 MHz................................................. 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz................................................... 2.7 to 5.5 V
[In low-speed mode].............................................. 2.7 to 5.5 V
Note. 12.5 MHz < f(X
IN
)
≤
16 MHz is not available in the fre-
• Power dissipation (QzROM version)
• In frequency/2 mode ..................................... Typ. 32 mW
(V
CC
= 5 V, f(X
IN
) = 12.5 MHz, Ta = 25°C)
• In low-speed mode ........................................ Typ. 18
µW
(V
CC
= 2.5 V, f(X
IN
) = stop, f(X
CIN
) = 32 kHz, Ta = 25°C)
• Power dissipation (Flash memory version)
• In frequency/2 mode ..................................... Typ. 20 mW
(V
CC
= 5 V, f(X
IN
) = 12.5 MHz, Ta = 25°C)
• In low-speed mode ...................................... Typ. 1.1 mW
(V
CC
= 2.7 V, f(X
IN
) = stop, f(X
CIN
) = 32 kHz, Ta = 25°C)
• Operating temperature range ...............................
−20
to 85°C
Flash Memory Mode
• Program/Erase voltage ............................. V
CC
= 2.7 to 5.5 V
• Program method ....................... Programming in unit of byte
• Erase method .................................................... Block erasing
• Program/Erase control by software command
quency/2 mode.
quency/2 mode.
APPLICATION
Household products, Consumer electronics, etc.
Rev.3.01 Aug 08, 2007
REJ03B0158-0301
Page 1 of 134
38D5 Group
P4
7
/S
RDY2
/(KW
3
)
P4
6
/S
CLK2
/(KW
2
)
P4
5
/S
OUT2
/(KW
1
)
P4
4
/S
IN2
/(KW
0
)
P4
3
/S
RDY1
P4
2
/S
CLK1
P4
1
/T
X
D
P4
0
/R
X
D
AV
SS
V
REF
P5
7
/AN
7
/ADKEY
0
P5
6
/AN
6
P5
5
/AN
5
P5
4
/AN
4
P5
3
/AN
3
P5
2
/AN
2
79
65
68
67
66
69
70
72
71
74
73
76
75
77
78
80
Rev.3.01 Aug 08, 2007
REJ03B0158-0301
PIN CONFIGURATION
(TOP VIEW)
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Fig. 1 Pin configuration (QFP Package)
Page 2 of 134
P5
1
/AN
1
/RTP
1
P5
0
/AN
0
/RTP
0
P6
7
/CNTR
1
/(LED
5
)
P6
6
/INT
10
/CNTR
0
/(LED
4
)
P6
5
/T
XOUT1
/(LED
3
)
P6
4
/INT
2
/(LED
2
)
P6
3
/T
XOUT2
/(LED
1
)
P6
2
/INT
00
/(LED
0
)
OSCSEL (Note
1)
M38D5XGXFP
M38D59FFFP
RESET
P6
1
/X
COUT
P6
0
/X
CIN
V
SS
X
IN
X
OUT
V
CC
P7
4
/PWM
1
/T
4OUT
P7
3
/PWM
0
/T
3OUT
P7
2
/T
2OUT
/CKOUT
V
L3
V
L2
P7
1
/C
2
/INT
11
P7
0
/C
1
/INT
01
V
L1
P2
0
/SEG
0
/(KW
4
)
P2
1
/SEG
1
/(KW
5
)
P2
2
/SEG
2
/(KW
6
)
P2
3
/SEG
3
/(KW
7
)
P2
4
/SEG
4
P2
5
/SEG
5
P2
6
/SEG
6
P2
7
/SEG
7
P0
0
/SEG
8
P0
1
/SEG
9
P0
2
/SEG
10
P0
3
/SEG
11
P0
4
/SEG
12
P0
5
/SEG
13
P0
6
/SEG
14
P0
7
/SEG
15
P1
0
/SEG
16
P1
1
/SEG
17
P1
2
/SEG
18
P1
3
/SEG
19
P1
4
/SEG
20
P1
5
/SEG
21
P1
6
/SEG
22
P1
7
/SEG
23
Package type : PRQP0080GB-A(80P6N-A)
27
25
26
32
28
39
40
36
34
35
37
38
31
29
30
33
P3
0
/SEG
24
P3
1
/SEG
25
P3
2
/SEG
26
P3
3
/SEG
27
P3
4
/SEG
28
P3
5
/SEG
29
P3
6
/SEG
30
P3
7
/SEG
31
COM
7
/SEG
32
COM
6
/SEG
33
COM
5
/SEG
34
COM
4
/SEG
35
COM
3
COM
2
COM
1
COM
0
Note 1:
CNV
SS
in flash
memory version
38D5 Group
P2
2
/SEG
2
/(KW
6
)
P2
3
/SEG
3
/(KW
7
)
P2
4
/SEG
4
P2
5
/SEG
5
P2
6
/SEG
6
P2
7
/SEG
7
P0
0
/SEG
8
P0
1
/SEG
9
P0
2
/SEG
10
P0
3
/SEG
11
P0
4
/SEG
12
P0
5
/SEG
13
P0
6
/SEG
14
P0
7
/SEG
15
P1
0
/SEG
16
P1
1
/SEG
17
P1
2
/SEG
18
PIN CONFIGURATION
(TOP VIEW)
P1
3
/SEG
19
43
P1
4
/SEG
20
42
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
P2
1
/SEG
1
/(KW
5
)
P2
0
/SEG
0
/(KW
4
)
P4
7
/S
RDY2
/(KW
3
)
P4
6
/S
CLK2
/(KW
2
)
P4
5
/S
OUT2
/(KW
1
)
P4
4
/S
IN2
/(KW
0
)
P4
3
/S
RDY1
P4
2
/S
CLK1
P4
1
/T
X
D
P4
0
/R
X
D
AV
SS
V
REF
P5
7
/AN
7
/ADKEY
0
P5
6
/AN
6
P5
5
/AN
5
P5
4
/AN
4
P5
3
/AN
3
P5
2
/AN
2
P5
1
/AN
1
/RTP
1
P5
0
/AN
0
/RTP
0
41
P1
5
/SEG
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
M38D5XGXHP
M38D59FFHP
P1
6
/SEG
22
P1
7
/SEG
23
P3
0
/SEG
24
P3
1
/SEG
25
P3
2
/SEG
26
P3
3
/SEG
27
P3
4
/SEG
28
P3
5
/SEG
29
P3
6
/SEG
30
P3
7
/SEG
31
COM
7
/SEG
32
COM
6
/SEG
33
COM
5
/SEG
34
COM
4
/SEG
35
COM
3
COM
2
COM
1
COM
0
V
L1
P7
0
/C
1
/INT
01
P6
4
/INT
2
/(LED
2
)
P6
3
/T
XOUT2
/(LED
1
)
P6
2
/INT
00
/(LED
0
)
OSCSEL (Note
1)
RESET
P6
1
/X
COUT
P6
0
/X
CIN
V
SS
X
IN
X
OUT
V
CC
P7
4
/PWM
1
/T
4OUT
P7
3
/PWM
0
/T
3OUT
V
L3
V
L2
P6
7
/CNTR
1
/(LED
5
)
P6
6
/INT
10
/CNTR
0
/(LED
4
)
P6
5
/T
XOUT1
/(LED
3
)
P7
2
/T
2OUT
/CKOUT
P7
1
/C
2
/INT
11
Note 1:
CNV
SS
in flash
memory version
Package type : PLQP0080KB-A(80P6Q-A)
Fig. 2 Pin configuration (LQFP package)
Rev.3.01 Aug 08, 2007
REJ03B0158-0301
Page 3 of 134
38D5 Group
Table 1
Performance overview (1)
Parameter
Function
71
0.32
µs
(Minimum instruction, Oscillation frequency 12.5 MHz)
16 MHz (Maximum)
(1)
ROM
RAM
32 K to 60 K bytes
1536 to 2048 bytes
60 K bytes
2048 bytes
2-bit
×
1
8-bit
×
7, 3-bit
×
1 (36 pins sharing SEG)
17 sources, 16 vectors (includes key input interrupt)
8-bit
×
4, 16-bit
×
2
8-bit
×
1 (UART or Clock-synchronized)
8-bit
×
1 (Clock-synchronized)
10-bit
×
2, 16-bit
×
1 (common to IGBT output)
10-bit
×
8 (operated in low-speed mode)
8-bit
×
1
32 bytes
×
2 vectors
6 (average current: 15 mA, peak current: 30 mA, total current: 90 mA)
Bias
Duty
Common output
Segment output
1/2, 1/3
2, 3, 4, 8
4/8
32/36
Built-in (connect to external ceramic resonator or on-chip oscillator)
Built-in (connect to external quartz-crystal oscillator)
f(X
IN
)
≤
12.5 MHz 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
4 MHz
f(X
IN
)
≤
2 MHz
In frequency/4 mode
f(X
IN
)
≤
16 MHz
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
4 MHz
In frequency/8 mode
f(X
IN
)
≤
16 MHz
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
4 MHz
In low-speed mode
4.0 to 5.5 V
2.0 to 5.5 V
1.8 to 5.5 V
4.5 to 5.5 V
2.0 to 5.5 V
1.8 to 5.5 V
4.5 to 5.5 V
2.0 to 5.5 V
1.8 to 5.5 V
1.8 to 5.5 V
f(X
IN
)
≤
12.5 MHz 4.5 to 5.5 V
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
4 MHz
In frequency/4 mode
In frequency/8 mode
In low-speed mode
f(X
IN
)
≤
16 MHz
f(X
IN
)
≤
8 MHz
f(X
IN
)
≤
16 MHz
f(X
IN
)
≤
8 MHz
4.0 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
2.7 to 5.5 V
4.5 to 5.5 V
2.7 to 5.5 V
2.7 to 5.5 V
Number of basic instructions
Instruction execution time
Oscillation frequency
Memory sizes
(QzROM version)
ROM
Memory sizes
(Flash memory version) RAM
Input port
I/O port
Interrupt
Timer
Serial I/O1
Serial I/O2
PWM
A/D converter
Watchdog timer
ROM correction function
LED direct drive port
LCD drive control
circuit
P7
0
, P7
1
P0-P6, P7
2
-P7
4
Main clock generating circuits
Sub-clock generating circuits
Power source voltage
(QzROM version)
In frequency/2 mode
(1)
Power source voltage In frequency/2 mode
(Flash memory version)
(1)
NOTE:
1. 12.5 MHz < f(X
IN
)
≤
16 MHz is not available in the frequency/2 mode.
Rev.3.01 Aug 08, 2007
REJ03B0158-0301
Page 4 of 134
38D5 Group
Table 2
Performance overview (2)
Parameter
Function
Std. 32 mW (Vcc = 5 V, f(X
IN
) = 12.5 MHz, Ta = 25°C)
Std. 18
µW
(Vcc = 2.5 V, f(X
IN
) = stop, f(X
CIN
) = 32 kHz, Ta = 25°C)
Std. 20 mW (Vcc = 5 V, f(X
IN
) = 12.5 MHz, Ta = 25°C)
Std. 1.1 mW (Vcc = 2.7 V, f(X
IN
) = stop, f(X
CIN
) = 32 kHz, Ta = 25°C)
V
CC
10 mA
-20 to 85°C
CMOS silicon gate
80-pin plastic molded LQFP/QFP
In frequency/2 mode
In low-speed mode
In frequency/2 mode
In low-speed mode
Input/Output withstand voltage
Output current
Power dissipation
(QzROM version)
Power dissipation
(Flash memory version)
Input/Output characteristics
Operating temperature range
Device structure
Package
Rev.3.01 Aug 08, 2007
REJ03B0158-0301
Page 5 of 134