256MB, 512MB, Registered DIMMs
Preliminary
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 256Mb F-die
72-bit ECC
Revision 0.6
October 2003
Rev. 0.6 Oct. 2003
256MB, 512MB, Registered DIMMs
Revision History
Revision 0.5 (Sep. 2003)
- Initial Release
Preliminary
DDR2 SDRAM
Revision 0.6 (Oct. 2003)
-
Removed D4 speed bin(400 4-4-4)
- Added operation temperature condition
- Changed setup/hold time values(tlS/tDS, tIH/tDH)
- Added notes for setup/hold time(tIS/tDS, tIH/tDH)
- Added tREFI values by T
CASE
(85°C/95°C)
Rev. 0.6 Oct. 2003
256MB, 512MB, Registered DIMMs
DDR2 Registered DIMM Ordering Information
Part Number
M393T3253FG0-CE6/D5/CC
M393T3253FG0-LE6/D5/CC
M393T6453FG0-CE6/D5/CC
M393T6453FG0-LE6/D5/CC
M393T6450FG0-CE6/D5/CC
M393T6450FG0-LE6/D5/CC
Density Organization
256MB
256MB
512MB
512MB
512MB
512MB
32Mx72
32Mx72
64Mx72
64Mx72
64Mx72
64Mx72
Component Composition
32Mx8(K4T56083QF)*9EA
32Mx8(K4T56083QF)*9EA
32Mx8(K4T56083QF)*18EA
32Mx8(K4T56083QF)*18EA
64Mx4(K4T56043QF)*18EA
64Mx4(K4T56043QF)*18EA
Preliminary
DDR2 SDRAM
Number of
Rank
1
1
2
2
1
1
Height
30mm
30mm
30mm
30mm
30mm
30mm
Note:
1. Speed bin is in order of CL-tRCD-tRP
Features
• Performance range
E6(DDR2-667)
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
667
5-5-5
D5(DDR2-533)
400
533
-
4-4-4
CC(DDR2-400)
400
400
-
3-3-3
Unit
Mbps
Mbps
Mbps
CK
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/pin, 333MHz f
CK
for 667Mb/sec/pin
• 4 Bank
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Refresh and Self Refresh
Average Refesh Period 7.8us at lower then T
CASE
85°C, 3.9us at 85°C < T
CASE
< 95
°C
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 64Mx4/32Mx8
Address Configuration
Organization
64Mx4(256Mb) based
Module
32Mx8(256Mb) based
Module
Row Address
A0-A12
A0-A12
Column Address
A0-A9,A11
A0-A9
Bank Address
BA0-BA1
BA0-BA1
Auto Precharge
A10
A10
Rev. 0.6 Oct. 2003
256MB, 512MB, Registered DIMMs
Pin Configurations (Front side/Back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Preliminary
DDR2 SDRAM
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
RESET
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
V
SS
DQ4
DQ5
V
SS
DM0/DQS9
NC/DQS9
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/DQS10
NC/DQS10
V
SS
RFU
RFU
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/DQS11
NC/DQS11
V
SS
DQ22
DQ23
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8
DQS8
V
SS
CB2
CB3
V
SS
V
DDQ
CKE0
V
DD
NC
NC/Err_Out
V
DDQ
A11
A7
V
DD
A5
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
V
SS
DQ28
DQ29
V
SS
DM3/DQS12
NC/DQS12
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8/DQS17
NC/DQS17
V
SS
CB6
CB7
V
SS
V
DDQ
CKE1
4
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
Front
A4
V
DDQ
A2
V
DD
Pin
181
182
183
184
KEY
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Back
V
DDQ
A3
A1
V
DD
CK0
CK0
V
DD
A0
V
DD
BA1
V
DDQ
RAS
S0
V
DDQ
ODT0
NC
V
DD
V
SS
DQ36
DQ37
V
SS
DM4/DQS13
NC/DQS13
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front
V
SS
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC(TEST)
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5/DQS14
NC/DQS14
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
RFU
RFU
V
SS
DM6/DQS15
NC/DQS15
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/DQS16
NC/DQS16
V
SS
DQ62
DQ63
V
SS
VDDSPD
SA0
SA1
V
SS
V
SS
V
DD
NC/Par_In
V
DD
A10/AP
BA0
V
DDQ
WE
CAS
V
DDQ
S1
4
ODT1
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
4. CKE1,S1 Pin is used for double side Registered DIMM.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin Description
Pin Name
CK0
CK0
CKE0, CKE1
RAS
CAS
WE
S0, S1
A0~A9, A11~A12
A10/AP
BA0, BA1
SCL
SDA
SA0~SA2
Par_In
Err_Out
RESET
Description
Clock Inputs, positive line
Clock inputs, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
DDR2 SDRAM Bank Address
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
SPD address
Parity bit for the Address and Control bus
Parity error found in the Address and Control bus
Register and PLL control pin
Pin Name
ODT0~ODT1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DQS0~DQS8
DM(0~8),DQS(9~17)
DQS9~DQS17
RFU
NC
TEST
V
DD
V
DDQ
V
SS
V
REF
V
DDSPD
On die termination
Data Input/Output
Description
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Masks / Data strobes (Read)
Data strobes (Read), negative line
Reserved for Future Use
No Connect
Memory bus test tool (Not Connect and Not Useable on
DIMMs)
Core Power
I/O Power
Ground
Input/Output Reference
SPD Power
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 0.6 Oct. 2003
256MB, 512MB, Registered DIMMs
Input/Output Functional Description
Symbol
CK0
CK0
CKE0~CKE1
Type
SSTL_1.8
SSTL_1.8
SSTL_1.8
Polarity
Function
Preliminary
DDR2 SDRAM
Positive Edge Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative Edge Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
Active High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating
the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when high. When
decoder is disabled, new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM
when both inputs are high.
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
Reference voltage for SSTL_18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
-
Selects which SDRAM bank of four is activated.
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP
is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, auto-
precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to
control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of
BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
Data and Check Bit Input/Output pins
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency
of one clock once the write command is registered into the SDRAM.
Power and ground for the DDR SDRAM input buffers and core logic
Positive Edge Positive line of the differential data strobe for input and output data.
Negative Edge Negative line of the differential data strobe for input and output data.
-
-
-
These signals are tied at the system planar to either V
SS
or V
DDSPD
to configure the serial SPD
EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be con-
nected from the SDA bus line to V
DDSPD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from
the SCL bus time to V
DDSPD
to act as a pullup.
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports
from 1.7 Volt to 3.6 Volt operation).
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low,
all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low
level (The PLL will remain synchronized with the input clock )
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
S0~S1
SSTL_1.8
Active Low
ODT0~ODT1
RAS, CAS, WE
V
REF
V
DDQ
BA0~BA1
SSTL_1.8
SSTL_1.8
Supply
Supply
SSTL_1.8
Active High
Active Low
A0~A9,A10/AP
A11~A12
SSTL_1.8
-
DQ0~63,
CB0~CB7
DM0~DM8
V
DD
, V
SS
DQS0~DQS17
DQS0~DQS17
SA0~SA2
SDA
SCL
V
DDSPD
SSTL_1.8
SSTL_1.8
Supply
SSTL_1.8
SSTL_1.8
-
Active High
Supply
RESET
Par_In
Err_Out
TEST
Rev. 0.6 Oct. 2003
电机驱动控制（Motor Control）
